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| 32 - bit arm ? cortex ? - m3 fm3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05646 rev.*c revised june 19, 2017 mb9a150rb series the mb9a150rb series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with low - power consumption mode and competitive cost . th ese s eries are based on the arm cortex - m3 processor with on - chip flash memory and sram, and have peripheral functions such as various t imers, adcs , and communication interfaces (uart, c sio, i 2 c). the products which are described in this data sheet are placed in to type 8 product categories in fm3 family p eripheral m anual . features 32 - bit arm cortex - m3 core ? processor version: r2p1 ? up to 40 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memory] ? dual o peration flas h memory ? dual operation flash memory has the upper bank and the lower bank. so, this series could implement erase, write and read operations for each bank simultaneously. ? main area: up to 512 kbytes (upto 496 kbytes upper bank + 16 kbytes lowe r bank) ? work area: 32 kbytes (lower bank) ? read cycle: 0 wait - cycle ? security function for code protection [sram] this series on - chip sram is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 32 kbyte s ? sram1: up to 32 kbyte s external bus interface ? supports sram, nor nand flash memory device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size: up to 256 mbytes ? supports address/data multiplex ? supports external rdy function multi - function s erial i nterface (max 16 channels ) ? 16 channels with 16 steps9 - bit fifo ? operation mode is selectable from the followings for each channel. ? uart ? csio ? i 2 c [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control: automatically control the transmission/reception by cts/rts (only ch.4) ? various error detection func tions available (parity errors, framing errors, and overrun errors) [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function available [i 2 c] standard - mode (max 100 kbps) / fast - mode (max 400 kbps) supported dma controller (8channels) the dma controller has an independent bus from the cpu, so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in perip herals ? transfer address area: 32 - bit (4 gbyte s ) ? transfer mode: block transfer/burst transfer/demand transfer ? transfer data type: byte/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536
document number: 002 - 05646 rev.*c page 2 of 147 mb9a150rb series a/d converter (max 24 channels) [ 12 - bit a/d converter ] ? successive approximation type ? built - in 2 unit s ? conversion time: 2 .0 s @ 2.7 v to 3.6 v ? priority conversion available (priority at 2 levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for p riority conversion: 4 steps) base timer (max 16 channels) operation mode is selectable from the followings for each channel . ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer g eneral - purpose i/o port this series can use its pin s as general - purpose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in . it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up control per pin ? capable of reading pin level directly ? built - in the port relocate function ? up to 103 high - speed general - purpose i/o ports@120 pin package ? some ports are 5 v tolerant i/o see list of pin function and i /o circuit type to confirm the corresponding pins. dual timer (32 - /16 - bit down co unter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each channel . ? free - running ? periodic (=reload) ? one - shot multi - function t imer the multi - function timer is composed of the follow ing blocks. ? 16 - bit free - run timer 3ch. ? input capture 4ch. ? output compare 6ch. ? a/d activati on compare 2 ch. ? waveform generator 3ch. ? 16 - bit ppg timer 3ch. the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function quadrature position/revolution counter (qprc) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use as the up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers hdmi - cec/remote control reception ( up to 2 channels ) hdmi - cec transmission ? header block a utomatic transmission by judging signal free ? generating status interrupt by detecting arbitration lost ? generating start, eom, ack automatical ly to output cec transmission by setting 1 byte data ? generating transmission status interrupt when transmitting 1 block (1 byte data and eom/ack) hdmi - cec reception ? automatic ack reply function available ? line error detection function available remote contr ol reception ? 4 bytes reception buffer ? repeat code detection function available real - time clock (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 00 to 99. ? the interrupt function with specifying date and time (year /month/day/hour/minute) is available. this function is also available by specifying only year, month, day, hour or minute. ? timer interrupt function after set time or each set time . ? capable of rewriting the time with continuing the time count. ? leap year automatic count is available. document number: 002 - 05646 rev.*c page 3 of 147 mb9a150rb series watch counter the watch counter is used for wake up from sleep and timer mode. interval timer: up to 64 s (max) @ sub clock : 32.768 khz external interrupt controller unit ? up to 24 external interrupt input pin s ? include one non - maskable interrupt (nmi) input pin watchdog t imer ( two channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a " hardware " watchdog and a " software " watchdog. the hardware watchdog timer is clocked by the built - in low - speed cr oscillator. therefore , the hardware watchdog is active in any low - power consumption modes except rtc, stop , deep standby rtc and deep standby stop modes . crc (cyclic redundancy check) accelera tor the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator pol ynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 clock and reset [clocks] selectable from five clock sources (2 external oscillator s, 2 built - in cr oscillator s, and main pll). ? main clock: 4 mhz to 48 mhz ? sub clock: 32.768 khz ? built - in high - speed cr clock: 4 mhz ? built - in low - speed cr clock: 100 khz ? main pll clock [resets] ? reset requests from initx pin ? power - on reset ? software reset ? watchdog timers reset ? low - voltage detection reset ? clock super visor reset clock super visor (csv) clocks gen erated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? if external clock failure (clock stop) is detected, reset is asserted. ? if external frequency anomaly is detected, interrupt or reset is asserted. low - voltage detect or (lvd) this series includes 2 - stage monitoring of voltage on the vcc pins. when the voltage falls below the voltage that has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - power consumption m ode six low - power consumption modes supported. ? sleep ? timer ? rtc ? stop ? deep standby rtc (selectable between k eeping the value of ram and not) ? deep standby stop (selectable between k eeping the value of ram and not) debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm) . * *: mb9af 154 m b , f 155mb and f 156 m b support only swj - dp. unique id unique value of the device ( 41 - bit ) is set. power supply wide range voltage: vcc = 1.65 v to 3.6 v document number: 002 - 05646 rev.*c page 4 of 147 mb9a150rb series contents features ................................ ................................ ................................ ................................ ................................ ................... 1 1. product lineup ................................ ................................ ................................ ................................ .............................. 6 1.1 memory s ize ................................ ................................ ................................ ................................ ................................ ... 6 1.2 function ................................ ................................ ................................ ................................ ................................ ......... 6 2. packages ................................ ................................ ................................ ................................ ................................ ........ 8 3. pin assignment ................................ ................................ ................................ ................................ .............................. 9 3.1 lqm120 ................................ ................................ ................................ ................................ ................................ ......... 9 3.2 lqi100 ................................ ................................ ................................ ................................ ................................ ......... 10 3.3 lqh080 ................................ ................................ ................................ ................................ ................................ ........ 11 3.4 lbc112 ................................ ................................ ................................ ................................ ................................ ........ 12 3.5 fdg096 ................................ ................................ ................................ ................................ ................................ ....... 13 4. list of pin function ................................ ................................ ................................ ................................ ..................... 14 4.1 list of pin numbers ................................ ................................ ................................ ................................ ...................... 14 4.2 list of pin functions ................................ ................................ ................................ ................................ ..................... 36 5. i/o circuit type ................................ ................................ ................................ ................................ ............................ 60 6. handling precautions ................................ ................................ ................................ ................................ .................. 65 6.1 precautions for product design ................................ ................................ ................................ ................................ ... 65 6.2 precautions for package mounting ................................ ................................ ................................ .............................. 66 6.3 precautions for use environment ................................ ................................ ................................ ................................ 68 7. handling devices ................................ ................................ ................................ ................................ ......................... 69 7.1 power supply pins ................................ ................................ ................................ ................................ ....................... 69 7.2 stabilizing power supply voltage ................................ ................................ ................................ ................................ 69 7.3 crystal oscillator circuit ................................ ................................ ................................ ................................ ............... 69 7.4 sub crystal oscillator ................................ ................................ ................................ ................................ .................. 69 7.5 using an external clock ................................ ................................ ................................ ................................ ................ 70 7.6 handling when using multi - function serial pin as i 2 c pin ................................ ................................ .............................. 70 7.7 c pin ................................ ................................ ................................ ................................ ................................ ............ 70 7.8 mode pins (md0) ................................ ................................ ................................ ................................ ......................... 70 7.9 notes on power - on ................................ ................................ ................................ ................................ ....................... 71 7.10 serial communication ................................ ................................ ................................ ................................ .................. 71 7.11 differences in features among the products with different memory sizes and between flash memory products and mask products ................................ ................................ ................................ ................................ ..................... 71 7.12 pull - up function of 5 v tolerant i/o ................................ ................................ ................................ ............................... 71 8. block diagram ................................ ................................ ................................ ................................ .............................. 72 9. memory size ................................ ................................ ................................ ................................ ............................... 72 10. memory map ................................ ................................ ................................ ................................ ................................ . 73 10.1 memory map (1) ................................ ................................ ................................ ................................ ........................... 73 10.2 memory map (2) ................................ ................................ ................................ ................................ ........................... 74 10.3 peripheral address map ................................ ................................ ................................ ................................ .............. 75 11. pin status in each cpu state ................................ ................................ ................................ ................................ ..... 76 11.1 list of pin status ................................ ................................ ................................ ................................ .......................... 77 12. electrical characteristics ................................ ................................ ................................ ................................ ............ 86 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 86 12.2 recommended operating conditions ................................ ................................ ................................ .......................... 87 12.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 88 12.3.1 current rating ................................ ................................ ................................ ................................ ............................... 88 document number: 002 - 05646 rev.*c page 5 of 147 mb9a150rb series 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 91 12.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 92 12.4.1 main clock input characteristics ................................ ................................ ................................ ................................ .. 92 12.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 93 12.4.3 built - in cr oscillation characteristics ................................ ................................ ................................ .......................... 94 12.4.4 ope rating conditions of main pll ................................ ................................ ................................ ............................... 95 12.4.5 reset input characteristics ................................ ................................ ................................ ................................ .......... 96 12.4.6 power - on reset timing ................................ ................................ ................................ ................................ ................ 96 12.4.7 external bus timing ................................ ................................ ................................ ................................ ..................... 97 12.4.8 base timer input timing ................................ ................................ ................................ ................................ ............ 108 12.4.9 csio/uart timing ................................ ................................ ................................ ................................ .................... 109 12.4.10 external input timing ................................ ................................ ................................ ................................ ............... 117 12.4.11 quadrature position/revolution counter timing ................................ ................................ ................................ ....... 118 12.4.12 i 2 c timing ................................ ................................ ................................ ................................ ................................ 121 12.4.13 etm timing ................................ ................................ ................................ ................................ .............................. 122 12.4.14 jtag timing ................................ ................................ ................................ ................................ ............................ 123 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ .................. 124 12.5.1 electrical characteristics for the a/d converter ................................ ................................ ................................ ......... 124 12.5.2 definition of 12 - bit a/d converter terms ................................ ................................ ................................ ................... 126 12.6 low - voltage detection characteristics ................................ ................................ ................................ ...................... 127 12.6.1 low - voltage detection reset ................................ ................................ ................................ ................................ ..... 127 12.6.2 interrupt of low - voltage detection ................................ ................................ ................................ ............................. 129 12.7 flash memory write/erase characteristics ................................ ................................ ................................ ................ 130 12.7.1 write / erase time ................................ ................................ ................................ ................................ ....................... 130 12.7.2 write cycles and data hold time ................................ ................................ ................................ ................................ . 130 12.8 return time from low - power consumption mode ................................ ................................ ................................ .... 131 12.8.1 return factor: interrupt/wkup ................................ ................................ ................................ ................................ .. 131 12.8.2 return factor: reset ................................ ................................ ................................ ................................ .................. 133 13. ordering information ................................ ................................ ................................ ................................ ................. 135 14. package dimensions ................................ ................................ ................................ ................................ ................. 136 15. errata ................................ ................................ ................................ ................................ ................................ .......... 141 15.1 part number s affected ................................ ................................ ................................ ................................ ............... 141 15.2 qualification status ................................ ................................ ................................ ................................ .................... 141 15.3 errata summary ................................ ................................ ................................ ................................ ......................... 141 16. major changes ................................ ................................ ................................ ................................ ........................... 143 document history ................................ ................................ ................................ ................................ ............................... 146 sales, sol utions, and legal information ................................ ................................ ................................ ........................... 147 document number: 002 - 05646 rev.*c page 6 of 147 mb9a150rb series 1. product lineup 1.1 memory size product name mb9af 154 m b /n b/rb mb9af 155 m b /n b/rb mb9af 156 m b /n b/rb on - chip flash memory main area 256 kbytes 384 kbytes 512 kbytes work area 32 kbytes 32 kbytes 32 kbytes on - chip sram sram0 16 kbytes 24 kbytes 32 kbytes sram1 16 kbytes 24 kbytes 32 kbytes total 32 kbytes 48 kbytes 64 kbytes 1.2 function product name mb9af154mb mb9af155mb mb9af156mb mb9af154nb mb9af155nb mb9af156nb mb9af154rb mb9af155rb mb9af156rb pin count 80 /96 100 /112 120 cpu cortex - m3 freq. 40 mhz power supply voltage range 1.65v to 3.6v dmac 8ch. external bus interface addr: 21 - bit (max) r/w data: 8 - bit (max) cs: 4 (max) support : sram , nor flash memory addr: 25 - bit (max) r/w data: 8 - /16 - bit (max) cs: 8 (max) support : sram , nor flash memory addr: 25 - bit (max) r/w data: 8 - /16 - bit (max) cs: 8 (max) support : sram , nor flash memory , nand flash memory multi - function serial interface (uart/csio/i 2 c) 10 ch. (max) enabled channels : ch.0 to ch.7, ch.10, ch.11 14 ch. (max) enabled channels : ch.0 to ch.13 16 ch. (max) enabled channels : ch.0 to ch.15 base timer (pwc/reload timer/pwm/ppg) 16 ch. (max) mf - timer a/d activation compare 2ch . 1 unit (max) input capture 4ch . free - run timer 3ch . output compare 6ch . waveform generator 3ch . ppg 3ch . qprc 2ch. (max) dual timer 1 unit hdmi - cec/ remote control reception 2ch. (max) document number: 002 - 05646 rev.*c page 7 of 147 mb9a150rb series product name mb9af154mb mb9af155mb mb9af156mb mb9af154nb mb9af155nb mb9af156nb mb9af154rb mb9af155rb mb9af156rb real - time clock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1ch. (sw) + 1ch. (hw) external interrupts 23 pins (max) + nmi 1 24 pins (max) + nmi 1 i/o ports 66 pins (max) 83 pins (max) 103 pins (max) 12 - bit a/d converter 1 7 ch . (2 unit s ) 24ch . (2 unit s ) csv (clock super visor) yes lvd (low - voltage detector) 2ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp swj - dp/etm unique id yes note: ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. ? see electrical characteristics 0 ac characteristics 12.4.3 built - in cr oscillation characteristics for accuracy of built - in cr . document number: 002 - 05646 rev.*c page 8 of 147 mb9a150rb series 2. packages product name package mb9af154mb mb9af 155mb mb9af156mb mb9af154nb mb9af155nb mb9af156nb mb9af154rb mb9af155rb mb9af156rb lqfp: lqh080 (0.5 mm pitch) ? - - bga: fdg096 (0.5 mm pitch) ? ? - - lqfp: lqi100 (0.5 mm pitch) - ? ? - bga: lbc112 (0.8 mm pitch) - ? ? - lqfp: lqm120 (0.5 mm pitch) - ? - ? ? ? ? : supported note: ? see package dimensions for detailed information on each package. document number: 002 - 05646 rev.*c page 9 of 147 mb9a150rb series 3. pin assignment 3.1 lqm120 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/tioa15_0/int17_1 p80/tiob15_0/int16_1 vcc p60/sin5_0/igtrg_1/tioa2_2/int15_1/wkup3/cec1_0/mrdy_0 p61/sot5_0/tiob2_2 p62/adtg_3/sck5_0/tioa15_1/int07_1/moex_0 p63/sin5_1/tiob15_1/int03_0/mwex_0 p64/sot5_1/tioa7_0/int10_2 p65/sck5_1/tiob7_0/tiob12_2/int23_0 p66/sin3_0/tioa12_2/int11_2 p67/sot3_0/tioa7_2/int22_0 p68/sck3_0/tiob7_2/int12_2 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0e/cts4_0/tiob3_2/int21_0/mdqm1_0 p0d/rts4_0/tioa3_2/int20_0/mdqm0_0 p0c/sck4_0/tioa6_1/int19_0/male_0 p0b/sot4_0/tiob6_1/int18_0/cec0_1/mcsx0_0 p0a/sin4_0/int00_2/wkup5/mcsx1_0 p09/traceclk/rts4_2/tiob0_2/int17_0/mcsx2_0 p08/an23/traced3/cts4_2/tioa0_2/int16_0/mcsx3_0 p07/an22/adtg_0/traced2/sck4_2/int23_1/mclkout_0 p06/an21/traced1/sot4_2/tiob5_2/int01_1/mcsx4_0 p05/an20/traced0/sin8_0/sin4_2/tioa5_2/int00_1/mcsx5_0 p04/tdo/swo p03/tms/swdio p02/tdi/sot8_0/tiob14_2/mcsx6_0 p01/tck/swclk p00/trstx/sck8_0/tioa14_2/mcsx7_0 vcc 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 vcc 1 90 vss p50/sin3_1/ain0_2/tiob8_0/int00_0/madata00_0 2 89 p20/an19/crout_0/ain1_1/tioa10_2/int05_0/mad24_0 p51/sot3_1/bin0_2/tiob9_0/int01_0/madata01_0 3 88 p21/an18/sin0_0/bin1_1/tiob10_2/int06_1/wkup2 p52/sck3_1/zin0_2/tiob10_0/int02_0/madata02_0 4 87 p22/an17/sot0_0/zin1_1/tiob7_1 p53/sin6_0/tiob11_0/tioa1_2/int07_2/madata03_0 5 86 p23/an16/sck0_0/rto00_1/tioa7_1 p54/sot6_0/tiob12_0/tiob1_2/int18_1/madata04_0 6 85 p24/sin2_1/rto01_1/tiob14_1/int01_2 p55/adtg_1/sck6_0/tiob13_0/int19_1/madata05_0 7 84 p25/sot2_1/rto02_1/tioa14_1/tiob11_2 p56/sin1_0/tioa8_0/int08_2/cec1_1/madata06_0 8 83 p26/sck2_1/rto03_1/tioa11_2 p57/sot1_0/tioa9_0/madata07_0 9 82 p27/sin15_0/rto04_1/tioa6_2/int02_2 p58/sck1_0/tioa10_0/madata08_0 10 81 p28/adtg_4/sot15_0/rto05_1/tiob6_2 p59/sin7_0/tioa11_0/int09_2/madata09_0 11 80 p1f/an15/adtg_5/sck15_0/frck0_1/tiob9_2/mad23_0 p5a/sot7_0/tioa12_0/int16_2/madata10_0 12 79 p1e/an14/rts4_1/dtti0x_1/tioa9_2/int23_2/mad22_0 p5b/sck7_0/tioa13_0/int17_2/madata11_0 13 78 p1d/an13/cts4_1/ic03_1/tioa13_1/int22_2/mad21_0 p30/ain0_0/tiob0_1/tioa13_2/int03_2/wkup4/madata12_0 14 77 p1c/an12/sck4_1/ic02_1/tioa12_1/int21_2/mad20_0 p31/sck6_1/bin0_0/tiob1_1/tiob13_2/int04_2/madata13_0 15 76 p1b/an11/sot4_1/ic01_1/tioa11_1/int20_2/mad19_0 p32/sot6_1/zin0_0/tiob2_1/int05_2/madata14_0 16 75 p1a/an10/sin4_1/ic00_1/tioa10_1/int05_1/mad18_0 p33/adtg_6/sin9_0/sin6_1/tiob3_1/int04_0/madata15_0 17 74 p19/an09/sck2_2/tioa9_1/mad17_0 p34/sot9_0/frck0_0/tiob4_1/tioa15_2/mnale_0 18 73 p18/an08/sot2_2/tioa8_1/mad16_0 p35/sck9_0/ic03_0/tiob5_1/tiob15_2/int08_1/mncle_0 19 72 avss p36/sin5_2/ic02_0/tiob14_0/int09_1/mnwex_0 20 71 avrh p37/sot5_2/ic01_0/tioa14_0/int10_1/mnrex_0 21 70 avcc p38/sck5_2/ic00_0/tioa8_2/int11_1 22 69 p17/an07/sin2_2/int04_1/mad15_0 p39/adtg_2/sin10_0/dtti0x_0/tiob8_2/int06_0 23 68 p16/an06/sck0_1/tiob13_1/int15_0/mad14_0 p3a/sot10_0/rto00_0/tioa0_1/int07_0/rtcco_2/subout_2 24 67 p15/an05/sot0_1/ic03_2/tiob12_1/int14_0/mad13_0 p3b/sck10_0/rto01_0/tioa1_1 25 66 p14/an04/sin0_1/ic02_2/tiob11_1/int03_1/mad12_0 p3c/sin11_0/rto02_0/tioa2_1/int18_2 26 65 p13/an03/sck1_1/ic01_2/tiob10_1/rtcco_1/subout_1/mad11_0 p3d/sot11_0/rto03_0/tioa3_1 27 64 p12/an02/sot1_1/ic00_2/tiob9_1/mad10_0 p3e/sck11_0/rto04_0/tioa4_1/int19_2 28 63 p11/an01/sin1_1/frck0_2/tiob8_1/int02_1/wkup1/mad09_0 p3f/rto05_0/tioa5_1 29 62 p10/an00 vss 30 61 vcc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vcc p40/sin12_0/tioa0_0/int12_1 p41/sot12_0/tioa1_0/int13_1 p42/sck12_0/tioa2_0/int08_0 p43/adtg_7/sin13_0/tioa3_0/int09_0 p44/sot13_0/tioa4_0/int10_0/mad00_0 p45/sck13_0/tioa5_0/int11_0/mad01_0 c vss vcc p46/x0a p47/x1a initx p48/sin3_2/int14_1/mad02_0 p49/sot3_2/ain0_1/tiob0_0/int20_1/mad03_0 p4a/sck3_2/bin0_1/tiob1_0/int21_1/mad04_0 p4b/igtrg_0/zin0_1/tiob2_0/int22_1/mad05_0 p4c/sck7_1/ain1_2/tiob3_0/int12_0/cec0_0/mad06_0 p4d/sot7_1/bin1_2/tiob4_0/int13_0/mad07_0 p4e/sin14_0/sin7_1/zin1_2/tiob5_0/int06_2/mad08_0 p70/sot14_0/tioa4_2 p71/sck14_0/tiob4_2/int13_2 p72/sin2_0/tioa6_0/int14_2 p73/sot2_0/tiob6_0/int15_2 p74/sck2_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 120 document number: 002 - 05646 rev.*c page 10 of 147 mb9a150rb series 3.2 lqi100 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/tioa15_0/int17_1 p80/tiob15_0/int16_1 vcc p60/sin5_0/igtrg_1/tioa2_2/int15_1/wkup3/cec1_0/mrdy_0 p61/sot5_0/tiob2_2 p62/adtg_3/sck5_0/tioa15_1/int07_1/moex_0 p63/tiob15_1/int03_0/mwex_0 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0e/cts4_0/tiob3_2/int21_0/mdqm1_0 p0d/rts4_0/tioa3_2/int20_0/mdqm0_0 p0c/sck4_0/tioa6_1/int19_0/male_0 p0b/sot4_0/tiob6_1/int18_0/cec0_1/mcsx0_0 p0a/sin4_0/int00_2/wkup5/mcsx1_0 p09/traceclk/rts4_2/tiob0_2/int17_0/mcsx2_0 p08/an23/traced3/cts4_2/tioa0_2/int16_0/mcsx3_0 p07/an22/adtg_0/traced2/sck4_2/int23_1/mclkout_0 p06/an21/traced1/sot4_2/tiob5_2/int01_1/mcsx4_0 p05/an20/traced0/sin8_0/sin4_2/tioa5_2/int00_1/mcsx5_0 p04/tdo/swo p03/tms/swdio p02/tdi/sot8_0/tiob14_2/mcsx6_0 p01/tck/swclk p00/trstx/sck8_0/tioa14_2/mcsx7_0 vcc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vcc 1 75 vss p50/sin3_1/ain0_2/tiob8_0/int00_0/madata00_0 2 74 p20/an19/crout_0/ain1_1/tioa10_2/int05_0/mad24_0 p51/sot3_1/bin0_2/tiob9_0/int01_0/madata01_0 3 73 p21/an18/sin0_0/bin1_1/tiob10_2/int06_1/wkup2 p52/sck3_1/zin0_2/tiob10_0/int02_0/madata02_0 4 72 p22/an17/sot0_0/zin1_1/tiob7_1 p53/sin6_0/tiob11_0/tioa1_2/int07_2/madata03_0 5 71 p23/an16/sck0_0/tioa7_1 p54/sot6_0/tiob12_0/tiob1_2/int18_1/madata04_0 6 70 p1f/an15/adtg_5/frck0_1/tiob9_2/mad23_0 p55/adtg_1/sck6_0/tiob13_0/int19_1/madata05_0 7 69 p1e/an14/rts4_1/dtti0x_1/tioa9_2/int23_2/mad22_0 p56/int08_2/cec1_1/madata06_0 8 68 p1d/an13/cts4_1/ic03_1/tioa13_1/int22_2/mad21_0 p30/ain0_0/tiob0_1/tioa13_2/int03_2/wkup4/madata07_0 9 67 p1c/an12/sck4_1/ic02_1/tioa12_1/int21_2/mad20_0 p31/sck6_1/bin0_0/tiob1_1/tiob13_2/int04_2/madata08_0 10 66 p1b/an11/sot4_1/ic01_1/tioa11_1/int20_2/mad19_0 p32/sot6_1/zin0_0/tiob2_1/int05_2/madata09_0 11 65 p1a/an10/sin4_1/ic00_1/tioa10_1/int05_1/mad18_0 p33/adtg_6/sin9_0/sin6_1/tiob3_1/int04_0/madata10_0 12 64 p19/an09/sck2_2/tioa9_1/mad17_0 p34/sot9_0/frck0_0/tiob4_1/tioa15_2/madata11_0 13 63 p18/an08/sot2_2/tioa8_1/mad16_0 p35/sck9_0/ic03_0/tiob5_1/tiob15_2/int08_1/madata12_0 14 62 avss p36/sin5_2/ic02_0/tiob14_0/int09_1/madata13_0 15 61 avrh p37/sot5_2/ic01_0/tioa14_0/int10_1/madata14_0 16 60 avcc p38/sck5_2/ic00_0/tioa8_2/int11_1/madata15_0 17 59 p17/an07/sin2_2/int04_1/mad15_0 p39/adtg_2/sin10_0/dtti0x_0/tiob8_2/int06_0 18 58 p16/an06/sck0_1/tiob13_1/int15_0/mad14_0 p3a/sot10_0/rto00_0/tioa0_1/int07_0/rtcco_2/subout_2 19 57 p15/an05/sot0_1/ic03_2/tiob12_1/int14_0/mad13_0 p3b/sck10_0/rto01_0/tioa1_1 20 56 p14/an04/sin0_1/ic02_2/tiob11_1/int03_1/mad12_0 p3c/sin11_0/rto02_0/tioa2_1/int18_2 21 55 p13/an03/sck1_1/ic01_2/tiob10_1/rtcco_1/subout_1/mad11_0 p3d/sot11_0/rto03_0/tioa3_1 22 54 p12/an02/sot1_1/ic00_2/tiob9_1/mad10_0 p3e/sck11_0/rto04_0/tioa4_1/int19_2 23 53 p11/an01/sin1_1/frck0_2/tiob8_1/int02_1/wkup1/mad09_0 p3f/rto05_0/tioa5_1 24 52 p10/an00 vss 25 51 vcc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vcc p40/sin12_0/tioa0_0/int12_1 p41/sot12_0/tioa1_0/int13_1 p42/sck12_0/tioa2_0/int08_0 p43/adtg_7/sin13_0/tioa3_0/int09_0 p44/sot13_0/tioa4_0/int10_0/mad00_0 p45/sck13_0/tioa5_0/int11_0/mad01_0 c vss vcc p46/x0a p47/x1a initx p48/sin3_2/int14_1/mad02_0 p49/sot3_2/ain0_1/tiob0_0/int20_1/mad03_0 p4a/sck3_2/bin0_1/tiob1_0/int21_1/mad04_0 p4b/igtrg_0/zin0_1/tiob2_0/int22_1/mad05_0 p4c/sck7_1/ain1_2/tiob3_0/int12_0/cec0_0/mad06_0 p4d/sot7_1/bin1_2/tiob4_0/int13_0/mad07_0 p4e/sin7_1/zin1_2/tiob5_0/int06_2/mad08_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 100 document number: 002 - 05646 rev.*c page 11 of 147 mb9a150rb series 3.3 lqh080 (top view) note : ? the number afte r the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/tioa15_0/int17_1 p80/tiob15_0/int16_1 vcc p60/sin5_0/igtrg_1/tioa2_2/int15_1/wkup3/cec1_0/mrdy_0 p61/sot5_0/tiob2_2 p62/adtg_3/sck5_0/tioa15_1/int07_1/moex_0 p63/tiob15_1/int03_0/mwex_0 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0e/cts4_0/tiob3_2/int21_0/mdqm1_0 p0d/rts4_0/tioa3_2/int20_0/mdqm0_0 p0c/sck4_0/tioa6_1/int19_0/male_0 p0b/sot4_0/tiob6_1/int18_0/cec0_1/mcsx0_0 p0a/sin4_0/int00_2/wkup5/mcsx1_0 p07/an22/adtg_0/int23_1/mclkout_0 p04/tdo/swo p03/tms/swdio p02/tdi/tiob14_2/mcsx6_0 p01/tck/swclk p00/trstx/tioa14_2/mcsx7_0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcc 1 60 p20/an19/crout_0/ain1_1/tioa10_2/int05_0/mad24_0 p50/sin3_1/ain0_2/tiob8_0/int00_0/madata00_0 2 59 p21/an18/sin0_0/bin1_1/tiob10_2/int06_1/wkup2 p51/sot3_1/bin0_2/tiob9_0/int01_0/madata01_0 3 58 p22/an17/sot0_0/zin1_1/tiob7_1 p52/sck3_1/zin0_2/tiob10_0/int02_0/madata02_0 4 57 p23/an16/sck0_0/tioa7_1 p53/sin6_0/tiob11_0/tioa1_2/int07_2/madata03_0 5 56 p1b/an11/sot4_1/ic01_1/tioa11_1/int20_2/mad19_0 p54/sot6_0/tiob12_0/tiob1_2/int18_1/madata04_0 6 55 p1a/an10/sin4_1/ic00_1/tioa10_1/int05_1/mad18_0 p55/adtg_1/sck6_0/tiob13_0/int19_1/madata05_0 7 54 p19/an09/sck2_2/tioa9_1/mad17_0 p56/int08_2/cec1_1/madata06_0 8 53 p18/an08/sot2_2/tioa8_1/mad16_0 p30/ain0_0/tiob0_1/tioa13_2/int03_2/wkup4/madata07_0 9 52 avss p31/sck6_1/bin0_0/tiob1_1/tiob13_2/int04_2/madata08_0 10 51 avrh p32/sot6_1/zin0_0/tiob2_1/int05_2/madata09_0 11 50 avcc p33/adtg_6/sin6_1/tiob3_1/int04_0/madata10_0 12 49 p17/an07/sin2_2/int04_1/mad15_0 p39/adtg_2/sin10_0/dtti0x_0/int06_0 13 48 p16/an06/sck0_1/tiob13_1/int15_0/mad14_0 p3a/sot10_0/rto00_0/tioa0_1/int07_0/rtcco_2/subout_2 14 47 p15/an05/sot0_1/ic03_2/tiob12_1/int14_0/mad13_0 p3b/sck10_0/rto01_0/tioa1_1 15 46 p14/an04/sin0_1/ic02_2/tiob11_1/int03_1/mad12_0 p3c/sin11_0/rto02_0/tioa2_1/int18_2 16 45 p13/an03/sck1_1/ic01_2/tiob10_1/rtcco_1/subout_1/mad11_0 p3d/sot11_0/rto03_0/tioa3_1 17 44 p12/an02/sot1_1/ic00_2/tiob9_1/mad10_0 p3e/sck11_0/rto04_0/tioa4_1/int19_2 18 43 p11/an01/sin1_1/frck0_2/tiob8_1/int02_1/wkup1/mad09_0 p3f/rto05_0/tioa5_1 19 42 p10/an00 vss 20 41 vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p44/tioa4_0/int10_0/mad00_0 p45/tioa5_0/int11_0/mad01_0 c vss vcc p46/x0a p47/x1a initx p48/sin3_2/int14_1/mad02_0 p49/sot3_2/ain0_1/tiob0_0/int20_1/mad03_0 p4a/sck3_2/bin0_1/tiob1_0/int21_1/mad04_0 p4b/igtrg_0/zin0_1/tiob2_0/int22_1/mad05_0 p4c/sck7_1/ain1_2/tiob3_0/int12_0/cec0_0/mad06_0 p4d/sot7_1/bin1_2/tiob4_0/int13_0/mad07_0 p4e/sin7_1/zin1_2/tiob5_0/int06_2/mad08_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 80 document number: 002 - 05646 rev.*c page 12 of 147 mb9a150rb series 3.4 lbc112 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. 1 2 3 4 5 6 7 8 9 10 11 a vss p81 p80 vcc p0e b vcc vss p52 p61 p0f p0c p08 tdo/ swo p0b p07 tms/ swdio trstx vcc vss tck/ swclk vss tdi vss p20 p21 d p53 p54 p55 vss an15 p56 p63 p0a vss p06 p23 c p50 p51 vss p60 p62 p0d p09 p05 an11 f p34 p35 p36 p39 an13 an10 an09 avrh e p30 p31 p32 p33 index p22 an14 an12 an07 an06 avss h p3b p3c p3e vss p44 p4c g p37 p38 p3a p3d an08 an05 vss an04 an03 avcc j vcc p3f vss p40 an00 k vcc vss x1a initx p42 p48 p4b p4e p43 p49 p4d an02 vss an01 p4a md0 x0 x1 vss md1 vss vcc l vss c x0a vss p41 p45 pfbga - 112 document number: 002 - 05646 rev.*c page 13 of 147 mb9a150rb series 3.5 fdg096 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same fun ction for the same channel. use the extended port function register (epfr) to select the pin. 1 2 3 4 5 6 7 8 9 10 11 a vss p81 p80 vcc vss b vcc vss p52 p61 p63 p0d p0c tdo/ swo p0f vss p07 tms/ swdio trstx vss tck/ swclk vss tdi vss p20 p21 d p53 p54 p55 index vss p22 p23 c p50 p51 vss p60 p62 p0e p0b p0a e p56 p30 p31 an11 an10 an09 an01 an00 an04 an08 an07 avrh g p32 p33 p39 an06 f vss vss vss an05 avss h p3a p3b p3c an03 avcc p49 p4c p4e md1 vss vcc k vcc vss x1a initx p45 j p3d p3e vss p3f p48 p4a p4d an02 vss vss p4b md0 x0 x1 vss l vss c x0a vss p44 pfbga - 96 document number: 002 - 05646 rev.*c page 14 of 147 mb9a150rb series 4. list of pin function 4.1 list of pin numbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for th ese pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 1 1 b1 1 b1 vcc - 2 2 c1 2 c1 p50 e k sin3_1 ain0_2 tiob8_0 int00_0 madata00_ 0 3 3 c2 3 c2 p51 e k sot3_1 (sda3_1) bin0_2 tiob9_0 int01_0 madata01_ 0 4 4 b3 4 b3 p52 e k sck3_1 (scl3_1) zin0_2 tiob10_0 int02_0 madata02_ 0 5 5 d1 5 d1 p53 e k sin6_0 tiob11_0 tioa1_2 int07_2 madata03_ 0 document number: 002 - 05646 rev.*c page 15 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 6 6 d2 6 d2 p54 e k sot6_0 (sda6_0) tiob12_0 tiob1_2 int18_1 madata04_ 0 7 7 d3 7 d3 p55 e k adtg_1 sck6_0 (scl6_0) tiob13_0 int19_1 madata05_ 0 8 8 d5 8 e1 p56 h [1] r int08_2 cec1_1 madata06_ 0 - - - - sin1_0 tioa8_0 9 - - - - p57 h [1] j sot1_0 (sda 1 _ 0 ) tioa9_0 madata07_0 10 - - - - p58 h [1] j sck1_0 (s cl1 _ 0 ) tioa10_0 madata08_0 document number: 002 - 05646 rev.*c page 16 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 11 - - - - p59 e k sin7_0 tioa11_0 int09_2 madata09_0 12 - - - - p5a e k sot7_0 (sda 7 _ 0 ) tioa12_0 int16_2 madata10_0 13 - - - - p5b e k sck7_0 (s cl7 _ 0 ) tioa13_0 int17_2 madata11_0 14 - - - - p30 e s ain0_0 tiob0_1 tioa13_2 int03_2 wkup4 madata 12 _ 0 - 9 e1 9 e2 p30 e s ain0_0 tiob0_1 tioa13_2 int03_2 wkup4 madata07_ 0 document number: 002 - 05646 rev.*c page 17 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 15 - - - - p31 e k sck6_1 (scl6_1) bin0_0 tiob1_1 tiob13_2 int04_2 madata 13 _ 0 - 10 e2 10 e3 p31 e k sck6_1 (scl6_1) bin0_0 tiob1_1 tiob13_2 int04_2 madata08_ 0 16 - - - - p32 e k sot6_1 (sda6_1) zin0_0 tiob2_1 int05_2 madata 14 _ 0 - 11 e3 11 g1 p32 e k sot6_1 (sda6_1) zin0_0 tiob2_1 int05_2 madata09_ 0 17 - - - - p33 e k adtg_6 sin9_0 sin6_1 tiob3_1 int04_0 madata1 5 _ 0 document number: 002 - 05646 rev.*c page 18 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 - 12 e4 12 g2 p33 e k adtg_6 sin6_1 tiob3_1 int04_0 madata10_ 0 - - sin9_0 18 - - - - p34 e j sot9_0 (sda 9 _ 0 ) frck0_0 tiob4_1 tioa15_2 mnale_0 - 13 f1 - - p34 e j sot9_0 (sda 9 _ 0 ) frck0_0 tiob4_1 tioa15_2 madata11_ 0 19 - - - - p35 e k sck9_0 (scl9_0) ic03_0 tiob5_1 tiob15_2 int08_1 mncle_0 - 14 f2 - - p35 e k sck9_0 (scl9_0) ic03_0 tiob5_1 tiob15_2 int08_1 madata12_ 0 document number: 002 - 05646 rev.*c page 19 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 20 - - - - p36 e k sin5_2 ic02_0 tiob14_0 int09_1 mnwex _ 0 - 15 f3 - - p36 e k sin5_2 ic02_0 tiob14_0 int09_1 madata13_ 0 - - - - f1 vss - - - - - f2 vss - - - - - f3 vss - 21 - - - - p37 e k sot5_2 (sda5_2) ic01_0 tioa14_0 int10_1 m nrex_0 - 16 g1 - - p37 e k sot5_2 (sda5_2) ic01_0 tioa14_0 int10_1 madata14_ 0 document number: 002 - 05646 rev.*c page 20 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 22 17 g2 - - p38 e k sck5_2 (scl5_2) ic00_0 tioa08_2 int11_1 - madata15_ 0 23 18 f4 13 g3 p39 e k adtg_2 sin10_0 dtti0x_0 int06_0 - - tiob8_2 24 19 g3 14 h1 p3a e k sot10_0 (sda10_0) rto00_0 tioa0_1 int07_0 rtcco_2 subout_2 25 20 h1 15 h2 p3b e j sck10_0 (scl10_0) rto01_0 tioa1_1 26 21 h2 16 h3 p3c e k sin11_0 rto02_0 tioa2_1 int18_2 document number: 002 - 05646 rev.*c page 21 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 27 22 g4 17 j1 p3d e j sot11_0 (sda11_0) rto03_0 tioa3_1 - - b2 - b2 vss - 28 23 h3 18 j2 p3e e k sck11_0 (scl11_0) rto04_0 tioa4_1 int19_2 29 24 j2 19 j4 p3f e j rto05_0 tioa5_1 30 25 l1 20 l1 vss - 31 26 j1 - - vcc - 32 27 j4 - - p40 e k sin12_0 tioa0_0 int12_1 33 28 l5 - - p41 e k sot12_0 (sda12_0) tioa1_0 int13_1 34 29 k5 - - p42 e k sck12_0 (scl12_0) tioa2_0 int08_0 document number: 002 - 05646 rev.*c page 22 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 35 30 j5 - - p43 e k adtg_7 sin13_0 tioa3_0 int09_0 36 31 h5 21 l5 p44 e k - - sot13_0 (sda13_0) 21 l5 tioa4_0 int10_0 mad00_ 0 37 32 l6 22 k5 p45 e k - - sck13_0 22 k5 tioa5_0 int11_0 mad01_ 0 - - k2 - k2 vss - - - j3 - j3 vss - - - h4 - - vss - - - - - l6 vss - 38 33 l2 23 l2 c - 39 34 l4 24 l4 vss - 40 35 k1 25 k1 vcc - 41 36 l3 26 l3 p46 d f x0a 42 37 k3 27 k3 p47 d g x1a 43 38 k4 28 k4 initx b c 44 39 k6 29 j5 p48 e k sin3_2 int14_1 mad02_ 0 document number: 002 - 05646 rev.*c page 23 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 45 40 j6 30 k6 p49 e k sot3_2 (sda3_2) ain0_1 tiob0_0 int20_1 mad03_ 0 46 41 l7 31 j6 p4a e k sck3_2 (scl3_2) bin0_1 tiob1_0 int21_1 mad04_ 0 47 42 k7 32 l7 p4b e k igtrg_0 zin0_1 tiob2_0 int22_1 mad05_ 0 48 43 h6 33 k7 p4c h [1] r sck7_1 (scl7_1) ain1_2 tiob3_0 int12_0 cec0 _0 mad06_ 0 document number: 002 - 05646 rev.*c page 24 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 49 44 j7 34 j7 p4d h [1] k sot7_1 (sda7_1) bin1_2 tiob4_0 int13_0 mad07_ 0 50 45 k8 35 k8 p4e h [1] k sin7_1 zin1_2 tiob5_0 int06_2 mad08_ 0 - - - - sin14_0 51 - - - - p70 e j sot14_0 (sda14_0) tioa4_2 52 - - - - p71 e k sck14_0 (scl14_0) tiob4_2 int13_2 53 - - - - p72 e k sin2_0 tioa6_0 int14_2 54 - - - - p73 e k sot2_0 (sda2_0) tiob6_0 int15_2 document number: 002 - 05646 rev.*c page 25 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 55 - - - - p74 e j sck2_0 (scl2_0) 56 46 k9 36 k9 md1 c e pe0 57 47 l8 37 l8 md0 g d 58 48 l9 38 l9 x0 a a pe2 59 49 l10 39 l10 x1 a b pe3 60 50 l11 40 l11 vss - 61 51 k11 41 k11 vcc - 62 52 j11 42 j11 p10 f l an00 63 53 j10 43 j10 p11 f p an01 sin1_1 frck0_2 tiob8_1 int02_1 wkup1 mad09_ 0 64 54 j8 44 j8 p12 f l an02 sot1_1 (sda1_1) ic00_2 tiob9_1 mad10_ 0 - - k10 - k10 vss - - - j9 - j9 vss - document number: 002 - 05646 rev.*c page 26 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 65 55 h10 45 h10 p13 f l an03 sck1_1 (scl1_1) ic01_2 tiob10_1 rtcco_1 subout_1 mad11_ 0 66 56 h9 46 h9 p14 f m an04 sin0_1 ic02_2 tiob11_1 int03_1 mad12_ 0 67 57 h7 47 g10 p15 f m an05 sot0_1 (sda0_1) ic03_2 tiob12_1 int14_0 mad13_ 0 document number: 002 - 05646 rev.*c page 27 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 68 58 g10 48 g9 p16 f m an06 sck0_1 (scl0_1) tiob13_1 int15_0 mad14_ 0 69 59 g9 49 f10 p17 f m an07 sin2_2 int04_1 mad15_ 0 70 60 h11 50 h11 avcc - 71 61 f11 51 f11 avrh - 72 62 g11 52 g11 avss - 73 63 g8 53 f9 p18 f l an08 sot2_2 (sda2_2) tioa8_1 mad16_ 0 74 64 f10 54 e11 p19 f l an09 sck2_2 (scl2_2) tioa9_1 mad17_ 0 - - h8 - - vss - 75 65 f9 55 e10 p1a f m an10 sin4_1 ic00_1 tioa10_1 int05_1 mad18_ 0 document number: 002 - 05646 rev.*c page 28 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 76 66 e11 56 e 9 p1b f m an11 sot4_1 (sda4_1) ic01_1 tioa11_1 int20_2 mad19_ 0 77 67 e10 - - p1c f m an12 sck4_1 (scl4_1) ic02_1 tioa12_1 int21_2 mad20_ 0 78 68 f8 - - p1d f m an13 cts4_1 ic03_1 tioa13_1 int22_2 mad21_ 0 79 69 e9 - - p1e f m an14 rts4_1 dtti0x_1 tioa9_2 int23_2 mad22_ 0 80 70 d11 - - p1f f l an15 adtg_5 frck0_1 tiob9_2 mad23_ 0 - - - - sck15_0 (scl15_0) - - b10 - b10 vss - document number: 002 - 05646 rev.*c page 29 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 - - c9 - c9 vss - - - - - d11 vss - 81 - - - - p2 8 e j a dtg_4 s ot15_ 0 (s da15 _0) rto05_1 tio b6 _ 2 82 - - - - p2 7 e k sin15_0 rto04_1 tioa6_2 int02_2 83 - - - - p2 6 e j sck2_1 (scl2_1) rto03_1 tioa11_2 84 - - - - p2 5 e j sot2_1 (sda2_1) rto02_1 tioa14_1 tiob11_2 85 - - - - p2 4 e k sin2_1 rto01_1 tiob14_1 int01_2 86 71 d10 57 d10 p23 f l an16 sck0_0 (scl0_0) tioa7_1 - - - - rto00_1 document number: 002 - 05646 rev.*c page 30 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 87 72 e8 58 d9 p22 f l an17 sot0_0 (sda0_0) zin1_1 tiob7_1 88 73 c11 59 c11 p21 f p an18 sin0_0 bin1_1 tiob10_2 int06_1 wkup2 89 74 c10 60 c10 p20 f m an19 crout_0 ain1_1 tioa10_2 int05_0 mad24_ 0 90 75 a11 - a11 vss - 91 76 a10 - - vcc - 92 77 a9 61 a 10 p00 e i trstx tioa14_2 mcsx7_ 0 - - sck8_0 (scl8_0) 93 78 b9 62 b9 p01 e i tck swclk 94 79 b11 63 b11 p02 e i tdi tiob14_2 mcsx6_ 0 - - sot8_0 document number: 002 - 05646 rev.*c page 31 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 95 80 a8 64 a9 p03 e i tms swdio 96 81 b8 65 b8 p04 e i tdo swo 97 82 c8 - - p05 f o an20 traced0 sin8_0 sin4_2 tioa5_2 int00_1 mcsx5_ 0 - - d8 - - vss - 98 83 d9 - - p06 f o an21 traced1 sot4_2 (sda4_2) tiob5_2 int01_1 mcsx4_ 0 99 84 a7 66 a8 p07 f o an22 adtg_0 mclkout_ 0 int23_1 - - traced2 sck4_2 (scl4_2) - - - - a7 vss - document number: 002 - 05646 rev.*c page 32 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 100 85 b7 - - p08 f o an23 traced3 cts4_2 tioa0_2 int16_0 mcsx3_ 0 101 86 c7 - - p09 e n traceclk rts4_2 tiob0_2 int17_0 mcsx2_ 0 102 87 d7 67 c8 p0a h [1] s sin4_0 int00_2 wkup5 mcsx1_ 0 103 88 a6 68 c7 p0b h [1] r sot4_0 (sda4_0) tiob6_1 int18_0 cec0_1 mcsx0_ 0 104 89 b6 69 b7 p0c h [1] k sck4_0 (scl4_0) tioa6_1 int19_0 male_ 0 - - d4 - - vss - document number: 002 - 05646 rev.*c page 33 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 - - c3 - c3 vss - 105 90 c6 70 b6 p0d e k rts4_0 tioa3_2 int20_0 mdqm0_ 0 106 91 a5 71 c6 p0e e k cts4_0 tiob3_2 int21_0 mdqm1_ 0 - - - - a5 vss - 107 92 b5 72 a6 p0f e h nmix crout_1 rtcco_0 subout_0 wkup0 108 - - - - p 68 e k sck3_0 (scl3_0) tiob7_2 int12_2 109 - - - - p 67 e k sot3_0 (sda3_0) tioa7_2 int22_0 110 - - - - p 66 e k sin3_0 tioa12_2 int11_2 document number: 002 - 05646 rev.*c page 34 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 111 - - - - p 65 e k sck5_1 (scl5_1) tiob7_0 tiob12_2 int23_0 112 - - - - p 64 e k sot5_1 (sda5_1) tioa7_0 int10_2 113 93 d6 73 b5 p63 e k tiob15_1 int03_0 mwex_ 0 - - - - sin5_1 114 94 c5 74 c5 p62 e k adtg_3 sck5_0 (scl5_0) tioa15_1 int07_1 moex_ 0 115 95 b4 75 b4 p61 e j sot5_0 (sda5_0) tiob2_2 116 96 c4 76 c4 p60 h [1] q sin5_0 igtrg_1 tioa2_2 int15_1 wkup3 cec1_0 mrdy_ 0 document number: 002 - 05646 rev.*c page 35 of 147 mb9a150rb series pin no pin name i/o circuit type pin state type lqfp - 1 2 0 lqfp - 100 bga - 112 lqfp - 80 bga - 96 117 97 a4 77 a4 vcc - 118 98 a3 78 a3 p80 e k tiob15_0 int16_1 119 99 a2 79 a2 p8 1 e k tioa15_0 int17_1 120 100 a1 80 a1 vss - [1]. 5v tolerant i/o document number: 002 - 05646 rev.*c page 36 of 147 mb9a150rb series 4.2 list of pin functions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr) to select the pin. p in function pin nam e function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 adc adtg_0 a/d converter external trigger input pin 99 84 a7 66 a8 adtg_1 7 7 d3 7 d3 adtg_2 23 18 f4 13 g3 adtg_3 114 94 c5 74 c5 adtg_4 81 - - - - adtg_5 80 70 d11 - - adtg_6 17 12 e4 12 g2 adtg_7 35 30 j5 - - adtg_8 - - - - - an00 a/d converter analog input pin . anxx describes adc ch.xx . 62 52 j11 42 j11 an01 63 53 j10 43 j10 an02 64 54 j8 44 j8 an03 65 55 h10 45 h10 an04 66 56 h9 46 h9 an05 67 57 h7 47 g10 an06 68 58 g10 48 g9 an07 69 59 g9 49 f10 an08 73 63 g8 53 f9 an09 74 64 f10 54 e11 an10 75 65 f9 55 e10 an11 76 66 e11 56 e9 an12 77 67 e10 - - an13 78 68 f8 - - an14 79 69 e9 - - an15 80 70 d11 - - an16 86 71 d10 57 d10 an17 87 72 e8 58 d9 an18 88 73 c11 59 c11 an19 89 74 c10 60 c10 an20 97 82 c8 - - an21 98 83 d9 - - an22 99 84 a7 66 a8 an23 100 85 b7 - - document number: 002 - 05646 rev.*c page 37 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 base timer 0 tioa0_0 base timer ch.0 tioa pin 32 27 j4 - - tioa0_1 24 19 g3 14 h1 tioa0_2 100 85 b7 - - tiob0_0 base timer ch.0 tiob pin 45 40 j6 30 k6 tiob0_1 14 9 e1 9 e2 tiob0_2 101 86 c7 - - base timer 1 tioa1_0 base timer ch.1 tioa pin 33 28 l5 - - tioa1_1 25 20 h1 15 h2 tioa1_2 5 5 d1 5 d1 tiob1_0 base timer ch.1 tiob pin 46 41 l7 31 j6 tiob1_1 15 10 e2 10 e3 tiob1_2 6 6 d2 6 d2 base timer 2 tioa2_0 base timer ch.2 tioa pin 34 29 k5 - - tioa2_1 26 21 h2 16 h3 tioa2_2 116 96 c4 76 c4 tiob2_0 base timer ch.2 tiob pin 47 42 k7 32 l7 tiob2_1 16 11 e3 11 g1 tiob2_2 115 95 b4 75 b4 base timer 3 tioa3_0 base timer ch.3 tioa pin 35 30 j5 - - tioa3_1 27 22 g4 17 j1 tioa3_2 105 90 c6 70 b6 tiob3_0 base timer ch.3 tiob pin 48 43 h6 33 k7 tiob3_1 17 12 e4 12 g2 tiob3_2 106 91 a5 71 c6 base timer 4 tioa4_0 base timer ch.4 tioa pin 36 31 h5 21 l5 tioa4_1 28 23 h3 18 j2 tioa4_2 51 - - - - tiob4_0 base timer ch.4 tiob pin 49 44 j7 34 j7 tiob4_1 18 13 f1 - - tiob4_2 52 - - - - base timer 5 tioa5_0 base timer ch.5 tioa pin 37 32 l6 22 k5 tioa5_1 29 24 j2 19 j4 tioa5_2 97 82 c8 - - tiob5_0 base timer ch.5 tiob pin 50 45 k8 35 k8 tiob5_1 19 14 f2 - - tiob5_2 98 83 d9 - - document number: 002 - 05646 rev.*c page 38 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 base timer 6 tioa 6 _0 base timer ch.6 tioa pin 53 - - - - tioa 6 _1 104 89 b6 69 b7 tioa 6 _2 82 - - - - tiob 6 _0 base timer ch.6 tiob pin 5 4 - - - - tiob 6 _1 103 88 a6 68 c7 tiob 6 _2 81 - - - - base timer 7 tioa7_0 base timer ch.7 tioa pin 112 - - - - tioa7_1 86 71 d10 57 d10 tioa7_2 109 - - - - tiob7_0 base timer ch.7 tiob pin 111 - - - - tiob7_1 87 72 e8 58 d9 tiob7_2 108 - - - - base timer 8 tioa8_0 base timer ch. 8 tioa pin 8 8 d5 8 e1 tioa8_1 73 63 g8 53 f9 tioa8_2 22 17 g2 - - tiob8_0 base timer ch. 8 tiob pin 2 2 c1 2 c1 tiob8_1 63 53 j10 43 j10 tiob8_2 23 18 f4 - - base timer 9 tioa9_0 base timer ch. 9 tioa pin 9 - - - - tioa9_1 74 64 f10 54 e11 tioa9_2 79 69 e9 - - tiob9_0 base timer ch. 9 tiob pin 3 3 c2 3 c2 tiob9_1 64 54 j8 44 j8 tiob9_2 80 70 d11 - - base timer 10 tioa10_0 base timer ch. 10 tioa pin 10 - - - - tioa10_1 75 65 f9 55 e10 tioa10_2 89 74 c10 60 c10 tiob10_0 base timer ch. 10 tiob pin 4 4 b3 4 b3 tiob10_1 65 55 h10 45 h10 tiob10_2 88 73 c11 59 c11 base timer 11 tioa11_0 base timer ch. 11 tioa pin 11 - - - - tioa11_1 76 66 e11 56 e9 tioa11_2 83 - - - - tiob11_0 base timer ch. 11 tiob pin 5 5 d1 5 d1 tiob11_1 66 56 h9 46 h9 tiob11_2 84 - - - - document number: 002 - 05646 rev.*c page 39 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 base timer 12 tioa12_0 base timer ch. 12 tioa pin 12 - - - - tioa12_1 77 67 e10 - - tioa12_2 110 - - - - tiob12_0 base timer ch. 12 tiob pin 6 6 d2 6 d2 tiob12_1 67 57 h7 47 g10 tiob12_2 111 - - - - base timer 13 tioa13_0 base timer ch. 13 tioa pin 13 - - - - tioa13_1 78 68 f8 - - tioa13_2 14 9 e1 9 e2 tiob13_0 base timer ch. 13 tiob pin 7 7 d3 7 d3 tiob13_1 68 58 g10 48 g9 tiob13_2 15 10 e2 10 e3 base timer 14 tioa14_0 base timer ch. 14 tioa pin 21 16 g1 - - tioa14_1 84 - - - - tioa14_2 92 77 a9 61 a10 tiob14_0 base timer ch. 14 tiob pin 20 15 f3 - - tiob14_1 85 - - - - tiob14_2 94 79 b11 63 b11 base timer 15 tioa15_0 base timer ch. 15 tioa pin 119 99 a2 79 a2 tioa15_1 114 94 c5 74 c5 tioa15_2 18 13 f1 - - tiob15_0 base timer ch. 15 tiob pin 118 98 a3 78 a3 tiob15_1 113 93 d6 73 b5 tiob15_2 19 14 f2 - - document number: 002 - 05646 rev.*c page 40 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 debugger swclk serial wire debug interface clock input pin 93 78 b9 62 b9 swdio serial wire debug interface data input / output pin 95 80 a8 64 a9 swo serial wire viewer output pin 96 81 b8 65 b8 tck jtag test clock input pin 93 78 b9 62 b9 tdi jtag test data input pin 94 79 b11 63 b11 tdo jtag debug data output pin 96 81 b8 65 b8 tms jtag test mode state input / output pin 95 80 a8 64 a9 traceclk trace clk output pin of etm 101 86 c7 - - traced0 trace data output pin of etm 97 82 c8 - - traced1 98 83 d9 - - traced2 99 84 a7 - - traced3 100 85 b7 - - trstx jtag test reset input pin 92 77 a9 61 a10 external bus mad00 _0 external bus interface address bus 36 31 h5 21 l5 mad01 _0 37 32 l6 22 k5 mad02 _0 44 39 k6 29 j5 mad03 _0 45 40 j6 30 k6 mad04 _0 46 41 l7 31 j6 mad05 _0 47 42 k7 32 l7 mad06 _0 48 43 h6 33 k7 mad07 _0 49 44 j7 34 j7 mad08 _0 50 45 k8 35 k8 mad09 _0 63 53 j10 43 j10 mad10 _0 64 54 j8 44 j8 mad11 _0 65 55 h10 45 h10 mad12 _0 66 56 h9 46 h9 mad13 _0 67 57 h7 47 g10 mad14 _0 68 58 g10 48 g9 mad15_0 69 59 g9 49 f10 mad16 _0 73 63 g8 53 f9 mad17 _0 74 64 f10 54 e11 mad18 _0 75 65 f9 55 e10 mad19 _0 76 66 e11 56 e9 mad20 _0 77 67 e10 - - mad21 _0 78 68 f8 - - mad2 2_0 79 69 e9 - - mad23 _0 80 70 d11 - - mad24 _0 89 74 c10 60 c10 document number: 002 - 05646 rev.*c page 41 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 external bus mcsx0 _0 external bus interface chip select output pin 103 88 a6 68 c7 mcsx1 _0 102 87 d7 67 c8 mcsx2 _0 101 86 c7 - - mcsx3 _0 100 85 b7 - - mcsx4 _0 98 83 d9 - - mcsx5 _0 97 82 c8 - - mcsx6 _0 94 79 b11 63 b11 mcsx7 _0 92 77 a9 61 a10 mdqm0 _0 external bus interface byte mask signal output pin 105 90 c6 70 b6 mdqm1 _0 106 91 a5 71 c6 moex _0 external bus interface read enable signal for sram 114 94 c5 74 c5 mwex _0 external bus interface write enable signal for sram 113 93 d6 73 b5 mnale_0 external bus interface ale signal to control nand flash memory output pin 18 - - - - mncle_0 external bus interface cle signal to control nand flash memory output pin 19 - - - - mnrex_0 external bus interface read enable signal to control nand flash memory 21 - - - - mnwex_0 external bus interface write enable signal to control nand flash memory 20 - - - - m a data0 0_0 e xternal bus interface data bus 2 2 c1 2 c1 m a data0 1_0 3 3 c2 3 c2 m a data0 2_0 4 4 b3 4 b3 m a data0 3_0 5 5 d1 5 d1 m a data0 4_0 6 6 d2 6 d2 m a data0 5_0 7 7 d3 7 d3 m a data0 6_0 8 8 d5 8 e1 m a data0 7_0 9 9 e1 9 e2 m a data0 8_0 10 10 e2 10 e3 m a data0 9_0 11 11 e3 11 g1 m a data 10_0 12 12 e4 12 g2 m a data 11_0 13 13 f1 - - m a data 12_0 14 14 f2 - - document number: 002 - 05646 rev.*c page 42 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 external bus m a data 13_0 15 15 f3 - - m a data 14_0 16 16 g1 - - m a data 15_0 17 17 g2 - - male_0 latch enable signal for multiplex 104 89 b6 69 b7 mrdy_0 external rdy input signal 116 96 c4 76 c4 mclkout_0 external bus clock output pin 99 84 a7 66 a8 external interrupt int00_0 external interrupt request 00 input pin 2 2 c1 2 c1 int00_1 97 82 c8 - - int00_2 102 87 d7 67 c8 int01_0 external interrupt request 0 1 input pin 3 3 c2 3 c2 int01_1 98 83 d9 - - int01_2 85 - - - - int02_0 external interrupt request 0 2 input pin 4 4 b3 4 b3 int02_1 63 53 j10 43 j10 int02_2 82 - - - - int03_0 external interrupt request 0 3 input pin 113 93 d6 73 b5 int03_1 66 56 h9 46 h9 int03_2 14 9 e1 9 e2 int04_0 external interrupt request 0 4 input pin 17 12 e4 12 g2 int04_1 69 59 g9 49 f10 int04_2 15 10 e2 10 e3 int05_0 external interrupt request 0 5 input pin 89 74 c10 60 c10 int05_1 75 65 f9 55 e10 int05_2 16 11 e3 11 g1 int06_0 external interrupt request 0 6 input pin 23 18 f4 13 g3 int06_1 88 73 c11 59 c11 int06_2 50 45 k8 35 k8 int07_0 external interrupt request 0 7 input pin 24 19 g3 14 h1 int07_1 114 94 c5 74 c5 int07_2 5 5 d1 5 d1 int08_0 external interrupt request 0 8 input pin 34 29 k5 - - int08_1 19 14 f2 - - int08_2 8 8 d5 8 e1 int09_0 external interrupt request 0 9 input pin 35 30 j5 - - int09_1 20 15 f3 - - int09_2 11 - - - - int10_0 external interrupt request 1 0 input pin 36 31 h5 21 l5 int10_1 21 16 g1 - - int10_2 112 - - - - int11_0 external interrupt request 11 input pin 37 32 l6 22 k5 int11_1 22 17 g2 - - int11_2 110 - - - - document number: 002 - 05646 rev.*c page 43 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 external interrupt int12_0 external interrupt request 12 input pin 48 43 h6 33 k7 int12_1 32 27 j4 - - int12_2 108 - - - - int13_0 external interrupt request 13 input pin 49 44 j7 34 j7 int13_1 33 28 l5 - - int13_2 52 - - - - int14_0 external interrupt request 14 input pin 67 57 h7 47 g10 int14_1 44 39 k6 29 j5 int14_2 53 - - - - int15_0 external interrupt request 15 input pin 68 58 g10 48 g9 int15_1 116 96 c4 76 c4 int15_2 54 - - - - int16_0 external interrupt request 16 input pin 100 85 b7 - - int16_1 118 98 a3 78 a3 int16_2 12 - - - - int17_0 external interrupt request 17 input pin 101 86 c7 - - int17_1 119 99 a2 79 a2 int17_2 13 - - - - int18_0 external interrupt request 18 input pin 103 88 a6 68 c7 int18_1 6 6 d2 6 d2 int18_2 26 21 h2 16 h3 int19_0 external interrupt request 19 input pin 104 89 b6 69 b7 int19_1 7 7 d3 7 d3 int19_2 28 23 h3 18 j2 int20_0 external interrupt request 20 input pin 105 90 c6 70 b6 int20_1 45 40 j6 30 k6 int20_2 76 66 e11 56 e9 int21_0 external interrupt request 21 input pin 106 91 a5 71 c6 int21_1 46 41 l7 31 j6 int21_2 77 67 e10 - - int22_0 external interrupt request 22 input pin 109 - - - - int22_1 47 42 k7 32 l7 int22_2 78 68 f8 - - int23_0 external interrupt request 23 input pin 111 - - - - int23_1 99 84 a7 66 a8 int23_2 79 69 e9 - - nmix non - maskable interrupt input pin 107 92 b5 72 a6 document number: 002 - 05646 rev.*c page 44 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 gpio p00 general - purpose i/o port 0 92 77 a9 61 a10 p01 93 78 b9 62 b9 p02 94 79 b11 63 b11 p03 95 80 a8 64 a9 p04 96 81 b8 65 b8 p05 97 82 c8 - - p06 98 83 d9 - - p07 99 84 a7 66 a8 p08 100 85 b7 - - p09 101 86 c7 - - p0a 102 87 d7 67 c8 p0b 103 88 a6 68 c7 p0c 104 89 b6 69 b7 p0d 105 90 c6 70 b6 p0e 106 91 a5 71 c6 p0f 107 92 b5 72 a6 p10 general - purpose i/o port 1 62 52 j11 42 j11 p11 63 53 j10 43 j10 p12 64 54 j8 44 j8 p13 65 55 h10 45 h10 p14 66 56 h9 46 h9 p15 67 57 h7 47 g10 p16 68 58 g10 48 g9 p17 69 59 g9 49 f10 p18 73 63 g8 53 f9 p19 74 64 f10 54 e11 p1a 75 65 f9 55 e10 p1b 76 66 e11 56 e9 p1c 77 67 e10 - - p1d 78 68 f8 - - p1e 79 69 e9 - - p1f 80 70 d11 - - p20 general - purpose i/o port 2 89 74 c10 60 c10 p21 88 73 c11 59 c11 p22 87 72 e8 58 d9 p23 86 71 d10 57 d10 p24 85 - - - - p25 84 - - - - p26 83 - - - - p27 82 - - - - p28 81 - - - - document number: 002 - 05646 rev.*c page 45 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 gpio p30 general - purpose i/o port 3 14 9 e1 9 e2 p31 15 10 e2 10 e3 p32 16 11 e3 11 g1 p33 17 12 e4 12 g2 p34 18 13 f1 - - p35 19 14 f2 - - p36 20 15 f3 - - p37 21 16 g1 - - p38 22 17 g2 - - p39 23 18 f4 13 g3 p3a 24 19 g3 14 h1 p3b 25 20 h1 15 h2 p3c 26 21 h2 16 h3 p3d 27 22 g4 17 j1 p3e 28 23 h3 18 j2 p3f 29 24 j2 19 j4 p40 general - purpose i/o port 4 32 27 j4 - - p41 33 28 l5 - - p42 34 29 k5 - - p43 35 30 j5 - - p44 36 31 h5 21 l5 p45 37 32 l6 22 k5 p46 41 36 l3 26 l3 p47 42 37 k3 27 k3 p48 44 39 k6 29 j5 p49 45 40 j6 30 k6 p4a 46 41 l7 31 j6 p4b 47 42 k7 32 l7 p4c 48 43 h6 33 k7 p4d 49 44 j7 34 j7 p4e 50 45 k8 35 k8 p50 general - purpose i/o port 5 2 2 c1 2 c1 p51 3 3 c2 3 c2 p52 4 4 b3 4 b3 p53 5 5 d1 5 d1 p54 6 6 d2 6 d2 p55 7 7 d3 7 d3 p56 8 8 d5 8 e1 p57 9 - - - - p58 10 - - - - p59 11 - - - - p5a 12 - - - - p5b 13 - - - - document number: 002 - 05646 rev.*c page 46 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 gpio p60 general - purpose i/o port 6 116 96 c4 76 c4 p61 115 95 b4 75 b4 p62 114 94 c5 74 c5 p6 3 113 93 d6 73 b5 p64 112 - - - - p65 111 - - - - p66 110 - - - - p67 109 - - - - p68 108 - - - - p70 general - purpose i/o port 7 51 - - - - p71 52 - - - - p72 53 - - - - p73 54 - - - - p74 55 - - - - p80 general - purpose i/o port 8 118 98 a3 78 a3 p81 119 99 a2 79 a2 pe0 general - purpose i/o port e 56 46 k9 36 k9 pe2 58 48 l9 38 l9 pe3 59 49 l10 39 l10 document number: 002 - 05646 rev.*c page 47 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 0 sin0_0 multi - function serial interface ch.0 input pin 88 73 c11 59 c11 sin0_1 66 56 h9 46 h9 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin . this pin operates as sot0 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda0 when it is used in an i 2 c (operation mode 4) . 87 72 e8 58 d9 sot0_1 (sda0_1) 67 57 h7 47 g10 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin . this pin operates as sck0 when it is used in a uart/csio (operation modes 0 to 2) and as scl0 when it is used in an i 2 c (operation mode 4) . 86 71 d10 57 d10 sck0_1 (scl0_1) 68 58 g10 48 g9 multi - function serial 1 sin1_0 multi - function serial interface ch. 1 input pin 8 - - - - sin1_1 63 53 j10 43 j10 sot1_ 0 (sda1_ 0 ) multi - function serial interface ch. 1 output pin . this pin operates as sot 1 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 1 when it is used in an i 2 c (operation mode 4) . 9 - - - - sot1_1 (sda1_1) 64 54 j8 44 j8 sck1_ 0 (scl1_ 0 ) multi - function serial interface ch. 1 clock i/o pin . this pin operates as sck 1 when it is used in a uart/csio (operation modes 0 to 2) and as scl 1 when it is used in an i 2 c (operation mode 4) . 10 - - - - sck1_1 (scl1_1) 65 55 h10 45 h10 document number: 002 - 05646 rev.*c page 48 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 2 sin2_ 0 multi - function serial interface ch. 2 input pin 53 - - - - sin2_ 1 85 - - - - sin2_ 2 69 59 g9 49 f10 sot2_ 0 (sda2_ 0 ) multi - function serial interface ch. 2 output pin . this pin operates as sot 2 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 2 when it is used in an i 2 c (operation mode 4) . 54 - - - - sot2_ 1 (sda2_ 1 ) 84 - - - - sot2_ 2 (sda2_ 2 ) 73 63 g8 53 f9 sck2_ 0 (scl2_ 0 ) multi - function serial interface ch. 2 clock i/o pin . this pin operates as sck 2 when it is used in a uart/csio (operation modes 0 to 2) and as scl 2 when it is used in an i 2 c (operation mode 4) . 55 - - - - sck2_ 1 (scl2_ 1 ) 83 - - - - sck2_ 2 (scl2_ 2 ) 74 64 f10 54 e11 multi - function serial 3 sin3_ 0 multi - function serial interface ch. 3 input pin 110 - - - - sin3_ 1 2 2 c1 2 c1 sin3_ 2 44 39 k6 29 j5 sot3_ 0 (sda3_ 0 ) multi - function serial interface ch. 3 output pin . this pin operates as sot 3 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 3 when it is used in an i 2 c (operation mode 4) . 109 - - - - sot3_ 1 (sda3_ 1 ) 3 3 c2 3 c2 sot3_ 2 (sda3_ 2 ) 45 40 j6 30 k6 sck3_ 0 (scl3_ 0 ) multi - function serial interface ch. 3 clock i/o pin . this pin operates as sck 3 when it is used in a uart/csio (operation modes 0 to 2) and as scl 3 when it is used in an i 2 c (operation mode 4) . 108 - - - - sck3_ 1 (scl3_ 1 ) 4 4 b3 4 b3 sck3_ 2 (scl3_ 2 ) 46 41 l7 31 j6 document number: 002 - 05646 rev.*c page 49 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 4 sin4_0 multi - function serial interface ch. 4 input pin 102 87 d7 67 c8 sin4_1 75 65 f9 55 e10 sin4_2 97 82 c8 - - sot4_0 (sda4_0) multi - function serial interface ch. 4 output pin . this pin operates as sot 4 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 4 when it is used in an i 2 c (operation mode 4) . 103 88 a6 68 c7 sot4_1 (sda4_1) 76 66 e11 56 e9 sot4_2 (sda4_2) 98 83 d9 - - sck4_0 (scl4_0) multi - function serial interface ch. 4 clock i/o pin . this pin operates as sck 4 when it is used in a uart/csio (operation modes 0 to 2) and as scl 4 when it is used in an i 2 c (operation mode 4) . 104 89 b6 69 b7 sck4_1 (scl4_1) 77 67 e10 - - sck4_2 (scl4_2) 99 84 a7 - - rts4_0 multi - function serial interface ch.4 rts output pin 105 90 c6 70 b6 rts4_1 79 69 e9 - - rts4_2 101 86 c7 - - cts4_0 multi - function serial interface ch.4 cts input pin 106 91 a5 71 c6 cts4_1 78 68 f8 - - cts4_2 100 85 b7 - - multi - function serial 5 sin5_0 multi - function serial interface ch. 5 input pin 116 96 c4 76 c4 sin5_ 1 113 - - - - sin5_2 20 15 f3 - - sot5_0 (sda5_0) multi - function serial interface ch. 5 output pin . this pin operates as sot 5 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 5 when it is used in an i 2 c (operation mode 4) . 115 95 b4 75 b4 sot5_ 1 (sda5_ 1 ) 112 - - - - sot5_2 (sda5_2) 21 16 g1 - - sck5_0 (scl5_0) multi - function serial interface ch. 5 clock i/o pin . this pin operates as sck 5 when it is used in a uart/csio (operation modes 0 to 2) and as scl 5 when it is used in an i 2 c (operation mode 4) . 114 94 c5 74 c5 sck5_ 1 (scl5_ 1 ) 11 1 - - - - sck5_2 (scl5_2) 22 17 g2 - - document number: 002 - 05646 rev.*c page 50 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 6 sin6_0 multi - function serial interface ch. 6 input pin 5 5 d1 5 d1 sin6_1 17 12 e4 12 g2 sot6_0 (sda6_0) multi - function serial interface ch. 6 output pin . this pin operates as sot 6 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 6 when it is used in an i 2 c (operation mode 4) . 6 6 d2 6 d2 sot6_1 (sda6_1) 16 11 e3 11 g1 sck6_0 (scl6_0) multi - function serial interface ch. 6 clock i/o pin . this pin operates as sck 6 when it is used in a uart/csio (operation modes 0 to 2) and as scl 6 when it is used in an i 2 c (operation mode 4) . 7 7 d3 7 d3 sck6_1 (scl6_1) 15 10 e2 10 e3 multi - function serial 7 sin7_ 0 multi - function serial interface ch. 7 input pin 11 - - - - sin7_ 1 50 45 k8 35 k8 sot7_ 0 (sda7_ 0 ) multi - function serial interface ch. 7 output pin . this pin operates as sot 7 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 7 when it is used in an i 2 c (operation mode 4) . 12 - - - - sot7_ 1 (sda7_ 1 ) 49 44 j7 34 j7 sck7_ 0 (scl7_ 0 ) multi - function serial interface ch. 7 clock i/o pin . this pin operates as sck 7 when it is used in a uart/csio (operation modes 0 to 2) and as scl 7 when it is used in an i 2 c (operation mode 4) . 13 - - - - sck7_ 1 (scl7_ 1 ) 48 43 h6 33 k7 document number: 002 - 05646 rev.*c page 51 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 8 sin 8 _0 multi - function serial interface ch. 8 input pin 97 82 c8 - - sot 8 _0 (sda 8 _0) multi - function serial interface ch. 8 output pin . this pin operates as sot 8 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 8 when it is used in an i 2 c (operation mode 4) . 94 79 b11 - - sck 8 _0 (scl 8 _0) multi - function serial interface ch. 8 clock i/o pin . this pin operates as sck 8 when it is used in a uart/csio (operation modes 0 to 2) and as scl 8 when it is used in an i 2 c (operation mode 4) . 92 77 a9 - - multi - function serial 9 sin 9 _0 multi - function serial interface ch. 9 input pin 17 12 e4 - - sot 9 _0 (sda 9 _0) multi - function serial interface ch. 9 output pin . this pin operates as sot 9 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 9 when it is used in an i 2 c (operation mode 4) . 18 13 f1 - - sck 9 _0 (scl 9 _0) multi - function serial interface ch. 9 clock i/o pin . this pin operates as sck 9 when it is used in a uart/csio (operation modes 0 to 2) and as scl 9 when it is used in an i 2 c (operation mode 4) . 19 14 f2 - - document number: 002 - 05646 rev.*c page 52 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 10 sin 10 _0 multi - function serial interface ch. 10 input pin 23 18 f4 13 g3 sot 10 _0 (sda 10 _0) multi - function serial interface ch. 10 output pin . this pin operates as sot 10 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 10 when it is used in an i 2 c (operation mode 4) . 24 19 g3 14 h1 sck 10 _0 (scl 10 _0) multi - function serial interface ch. 10 clock i/o pin . this pin operates as sck 10 when it is used in a uart/csio (operation modes 0 to 2) and as scl 10 when it is used in an i 2 c (operation mode 4) . 25 20 h1 15 h2 multi - function serial 11 sin 11 _0 multi - function serial interface ch. 11 input pin 26 21 h2 16 h3 sot 11 _0 (sda 11 _0) multi - function serial interface ch. 11 output pin . this pin operates as sot 11 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 11 when it is used in an i 2 c (operation mode 4) . 27 22 g4 17 j1 sck 11 _0 (scl 11 _0) multi - function serial interface ch. 11 clock i/o pin . this pin operates as sck 11 when it is used in a uart/csio (operation modes 0 to 2) and as scl 11 when it is used in an i 2 c (operation mode 4) . 28 23 h3 18 j2 document number: 002 - 05646 rev.*c page 53 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 12 sin 12 _0 multi - function serial interface ch. 12 input pin 32 27 j4 - - sot 12 _0 (sda 12 _0) multi - function serial interface ch. 12 output pin . this pin operates as sot 12 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 12 when it is used in an i 2 c (operation mode 4) . 33 28 l5 - - sck 12 _0 (scl 12 _0) multi - function serial interface ch. 12 clock i/o pin . this pin operates as sck 12 when it is used in a uart/csio (operation modes 0 to 2) and as scl 12 when it is used in an i 2 c (operation mode 4) . 34 29 k5 - - multi - function serial 13 sin 13 _0 multi - function serial interface ch. 13 input pin 35 30 j5 - - sot 13 _0 (sda 13 _0) multi - function serial interface ch. 13 output pin . this pin operates as sot 13 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 13 when it is used in an i 2 c (operation mode 4) . 36 31 h5 - - sck 13 _0 (scl 13 _0) multi - function serial interface ch. 13 clock i/o pin . this pin operates as sck 13 when it is used in a uart/csio (operation modes 0 to 2) and as scl 13 when it is used in an i 2 c (operation mode 4) . 37 32 l6 - - document number: 002 - 05646 rev.*c page 54 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function serial 14 sin 14 _0 multi - function serial interface ch. 14 input pin 50 - - - - sot 14 _0 (sda 14 _0) multi - function serial interface ch. 14 output pin . this pin operates as sot 14 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 14 when it is used in an i 2 c (operation mode 4) . 51 - - - - sck 14 _0 (scl 14 _0) multi - function serial interface ch. 14 clock i/o pin . this pin operates as sck 14 when it is used in a uart/csio (operation modes 0 to 2) and as scl 14 when it is used in an i 2 c (operation mode 4) . 52 - - - - multi - function serial 15 sin 15 _0 multi - function serial interface ch. 15 input pin 82 - - - sot 15 _0 (sda 15 _0) multi - function serial interface ch. 15 output pin . this pin operates as sot 15 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda 15 when it is used in an i 2 c (operation mode 4) . 81 - - - sck 15 _0 (scl 15 _0) multi - function serial interface ch. 15 clock i/o p in . this pin operates as sck 15 when it is used in a uart/csio (operation modes 0 to 2) and as scl 15 when it is used in an i 2 c (operation mode 4) . 80 - - - document number: 002 - 05646 rev.*c page 55 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function timer 0 dtti0x_0 input signal of waveform generator to control outputs rto00 to rto05 of multi - function timer 0 . 23 18 f4 13 g3 dtti0x_1 79 69 e9 - - frck0_0 16 - bit free - run timer ch.0 external clock input pin 18 13 f1 - - frck0_1 80 70 d11 - - frck0_ 2 63 53 j10 43 j10 ic00_0 16 - bit input capture input pin of multi - function timer 0. icxx describes channel number. 22 17 g2 - - ic00_1 75 65 f9 55 e10 ic00_ 2 64 54 j8 44 j8 ic01_0 21 16 g1 - - ic01_1 76 66 e11 56 e9 ic01_ 2 65 55 h10 45 h10 ic02_0 20 15 f3 - - ic02_1 77 67 e10 - - ic02_ 2 66 56 h9 46 h9 ic03_0 19 14 f2 - - ic03_1 78 68 f8 - - ic03_ 2 67 57 h7 47 g10 document number: 002 - 05646 rev.*c page 56 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 multi - function timer 0 rto00_0 (ppg00_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode . 24 19 g3 14 h1 rto00_1 (ppg00_1) 86 71 d10 57 d10 rto01_0 (ppg00_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode . 25 20 h1 15 h2 rto01_1 (ppg00_1) 85 - - - - rto02_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode . 26 21 h2 16 h3 rto02_1 (ppg02_1) 84 - - - - rto03_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode . 27 22 g4 17 j1 rto03_1 (ppg02_1) 83 - - - - rto04_0 (ppg04_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode . 28 23 h3 18 j2 rto04_1 (ppg04_1) 82 - - - - rto05_0 (ppg04_0) waveform generator output pin of multi - function timer 0. this pin operates as ppg04 when it is used in ppg0 output mode . 29 24 j2 19 j4 rto05_1 (ppg04_1) 81 - - - - igtrg_0 ppg igmt mode external trigger input pin 46 41 l7 31 j6 igtrg_1 116 96 c4 76 c4 document number: 002 - 05646 rev.*c page 57 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 quadrature position/ revolution counter 0 ain0_0 q prc ch.0 ain input pin 14 9 e1 9 e2 ain0_1 45 40 j6 30 k6 ain0_2 2 2 c1 2 c1 bin0_0 q prc ch.0 b in input pin 15 10 e2 10 e3 bin0_1 46 41 l7 31 j6 bin0_2 3 3 c2 3 c2 zin0_0 q prc ch.0 z in input pin 16 11 e3 11 g1 zin0_1 47 42 k7 32 l7 zin0_2 4 4 b3 4 b3 quadrature position/ revolution counter 1 ain1_1 q prc ch. 1 ain input pin 89 74 c10 60 c10 ain1_2 48 43 h6 33 k7 bin1_1 q prc ch. 1 b in input pin 88 73 c11 59 c11 bin1_2 49 44 j7 34 j7 zin1_1 q prc ch. 1 z in input pin 87 72 e8 58 d9 zin1_2 50 45 k8 35 k8 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 107 92 b5 72 a6 rtcco_1 65 55 h10 45 h10 rtcco_2 24 19 g3 14 h1 subout_ 0 sub clock output pin 107 92 b5 72 a6 subout_ 1 65 55 h10 45 h10 subout_ 2 24 19 g3 14 h1 low - power consumption mode wkup0 deep standby mode return signal input pin 0 107 92 b5 72 a6 wkup1 deep standby mode return signal input pin 1 63 53 j10 43 j10 wkup2 deep standby mode return signal input pin 2 88 73 c11 59 c11 wkup3 deep standby mode return signal input pin 3 116 96 c4 76 c4 wkup 4 deep standby mode return signal input pin 4 14 9 e1 9 e2 wkup 5 deep standby mode return signal input pin 5 102 87 d7 67 c8 hdmi - cec/ remote control reception cec0 _0 hdmi - cec/remote control reception ch.0 input/output pin 48 43 h6 33 k7 cec0_1 103 88 a6 68 c7 cec1_0 hdmi - cec/remote control reception ch.1 input/output pin 116 96 c4 76 c4 cec1 _1 8 8 d5 8 e1 document number: 002 - 05646 rev.*c page 58 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 reset initx external reset input pin. a reset is valid when initx=l. 43 38 k4 28 k4 mode md0 mode 0 pin. during normal operation, md0=l must be input. during serial programming to f lash memory, md0=h must be input. 57 47 l8 37 l8 md1 mode 1 pin. during serial programming to f lash memory, md1=l must be input. 56 46 k9 36 k9 power vcc power supply pin 1 1 b1 1 b1 vcc power supply pin 31 26 j1 - - vcc power supply pin 40 35 k1 25 k1 vcc power supply pin 61 51 k11 41 k11 vcc power supply pin 91 76 a10 - - vcc power supply pin 117 97 a4 77 a4 gnd vss gnd pin - - - - f1 vss gnd pin - - - - f2 vss gnd pin - - - - f3 vss gnd pin - - b2 - b2 vss gnd pin 30 25 l1 20 l1 vss gnd pin - - k2 - k2 vss gnd pin - - j3 - j3 vss gnd pin - - h4 - - vss gnd pin - - - - l6 vss gnd pin 39 34 l4 24 l4 vss gnd pin 60 50 l11 40 l11 vss gnd pin - - k10 - k10 vss gnd pin - - j9 - j9 vss gnd pin - - h8 - - vss gnd pin - - b10 - b10 vss gnd pin - - c9 - c9 vss gnd pin - - - - d11 vss gnd pin 90 75 a11 - a11 vss gnd pin - - d8 - - vss gnd pin - - - - a7 vss gnd pin - - d4 - - vss gnd pin - - c3 - c3 vss gnd pin - - - - a5 vss gnd pin 120 100 a1 80 a1 document number: 002 - 05646 rev.*c page 59 of 147 mb9a150rb series p in function pin name function description pin no lqfp - 120 lqfp - 100 bga - 112 lqfp - 80 bga - 96 clock x0 main clock (oscillation) input pin 58 48 l9 38 l9 x0a sub clock (oscillation) input pin 41 36 l3 26 l3 x1 main clock (oscillation) i/o pin 59 49 l10 39 l10 x1a sub clock (oscillation) i/o pin 42 37 k3 27 k3 crout _0 built - in high - speed cr - osc clock output port 89 74 c10 60 c10 crout _1 107 92 b5 72 a6 adc power avcc a/d converter analog power supply pin 70 60 h11 50 h11 avrh a/d converter analog reference voltage input pin 71 61 f11 51 f11 adc gnd avss a/d converter gnd pin 72 62 g11 52 g11 c pin c power stabilization capacity pin 38 33 l2 23 l2 note: ? while this device contains a test access port (tap) based on the ieee 1149.1 - 2001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other devices with different functionality. the tap pins may also be configurable for purposes other than access to the tap controller. document number: 002 - 05646 rev.*c page 60 of 147 mb9a150rb series 5. i /o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor: approximately 1 m ? with s tandby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control document number: 002 - 05646 rev.*c page 61 of 147 mb9a150rb series type circuit remarks b ? cmos level hysteresis input ? pull - up resistor: approximately 33 k c ? open drain output ? cmos level hysteresis input pull - up resistor digital in put digital input digital out put n-ch document number: 002 - 05646 rev.*c page 62 of 147 mb9a150rb series type circuit remarks d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis i nput ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control document number: 002 - 05646 rev.*c page 63 of 147 mb9a150rb series type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 33 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor cont rol digital input standby mode c ontrol analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r document number: 002 - 05646 rev.*c page 64 of 147 mb9a150rb series type circuit remarks g cmos level hysteresis input h ? cmos level output ? cmos level hysteresis input ? 5 v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off mode input digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r document number: 002 - 05646 rev.*c page 65 of 147 mb9a150rb series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observ ed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in e xcess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical chara cteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is mad e with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins the se precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins uncon nected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuousl y at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening , do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. document number: 002 - 05646 rev.*c page 66 of 147 mb9a150rb series ? obser vance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from suc h failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution : customers considering the use of our products in special applications where failure or abnormal operation may directly affec t human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc .) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or sur face mount type. in either case, for heat resistance during soldering, you should only mount under cypress ' recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead ins ertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform t o cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface tre atment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has establ ished a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. document number: 002 - 05646 rev.*c page 67 of 147 mb9a150rb series ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted us ing sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion o f moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for bak ing. condition: 125 c /24 h ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avo id the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. document number: 002 - 05646 rev.*c page 68 of 147 mb9a150rb series 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for rel iable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for en vironments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to sm oke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives. document number: 002 - 05646 rev.*c page 69 of 147 mb9a150rb series 7. handling devices 7.1 power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between each power supply pin and gnd pin, between avcc pin and avss pin near this device. 7.2 stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommende d operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. 7.3 crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operat ion. evaluate oscillation of your using crystal oscillator by your mount board. 7.4 sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommend ed for sub crystal oscillator to stabilize the oscillation. ? surface mount type size : more than 3.2 mm 1.5 mm load capacitance : approximately 6 pf to 7 pf ? lead type load capacitance : approximately 6 pf to 7 pf document number: 002 - 05646 rev.*c page 70 of 147 mb9a150rb series 7.5 using an external clock when using an external clock as an input of the main clock, set x0 / x1 to the external clock input, and input the clock to x0 . x1 (pe3) can be used as a general - purpose i/o port. similarly, w hen using an external clock as an input of the sub clock, set x0 a/ x1 a to the exte rnal clock input, and input the clock to x0 a. x1 a (p47) can be used as a general - purpose i/o port. 7.6 handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disabled. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. 7.7 c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor o r a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteris tics and y5v characteristics). please sele ct the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. 7.8 mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistor stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connect ion impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. example of using an external clock device x0 ( x0a ) x1(pe3), x1a (p47) can be used as general - purpose i/o ports. device c vss c s gnd set as external clock input document number: 002 - 05646 rev.*c page 71 of 147 mb9a150rb series 7.9 notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter, connect avcc = vcc and avss = vss. turning on : vcc 7.10 serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. 7.11 differences in features among the products with different memory sizes and between flash memory products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and os cillation characteristics among the products with different memory sizes and between flash memory products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. 7.12 pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i / o. document number: 002 - 05646 rev.*c page 72 of 147 mb9a150rb series 8. block diagram *: for the mb9af154mb, mb9af155mb, and mb9af156mb, etm is not available. 9. memory size see memory size in product lineup to confirm the memory size. c o r t e x - m 3 f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . w a t c h c o u n t e r u n i t 0 c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 2 4 - p i n + n m i p o w e r - o n r e s e t s r a m 0 1 6 / 2 4 / 3 2 k b y t e s r a m 1 1 6 / 2 4 / 3 2 k b y t e i d s y s c l k n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y u n i t 1 t r s t x , t c k , t d i , t m s t r a c e d x , t r a c e c l k x 0 a v c c , a v s s , a v r h a n x x t i o a x t i o b x c t d o x 1 x 0 a x 1 a s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , . . . p e x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r c r c a c c e l e r a t o r a d t g x r t s 4 c t s 4 m a d x m a d a t a x o n - c h i p f l a s h 2 5 6 + 3 2 k b y t e / 3 8 4 + 3 2 k b y t e / 5 1 2 + 3 2 k b y t e m u l t i - f u n c t i o n s e r i a l i / f 1 6 c h . h w f l o w c o n t r o l ( c h . 4 ) e x t e r n a l b u s i / f g p i o p i n - f u n c t i o n - c t r l l v d t p i u * r o m t a b l e e t m * s w j - d p m a i n o s c p l l s u b o s c c r 4 m h z c r 1 0 0 k h z c e c 0 , c e c 1 l v d c t r l b a s e t i m e r 1 6 - b i t 1 6 c h . / 3 2 - b i t 8 c h . h d m i - c e c / r e m o t e r e c i v e r c o n t r o l r e a l - t i m e c l o c k r t c c o , s u b o u t d e e p s t a n d b y c t r l w k u p x 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . a / d a c t i v a t i o n c o m p a r e 2 c h . 1 6 - b i t p p g 3 c h . d t t i 0 x f r c k 0 q p r c 2 c h . b i n x z i n x i c 0 x r t o 0 x a i n x 1 2 - b i t a / d c o n v e r t e r m u l t i - f u n c t i o n t i m e r 1 m c s x x , m d q m x , m o e x , m w e x , m a l e , m r d y , m n a l e , m n c l e , m n w e x , m n r e x , m c l k o u t i g t r g w a v e f o r m g e n e r a t o r 3 c h . c r o u t s o u r c e c l o c k a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) a h b - a h b b r i d g e a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z ) m u l t i - l a y e r a h b ( m a x 4 0 m h z ) document number: 002 - 05646 rev.*c page 73 of 147 mb9a150rb series 10. memory map 10.1 memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0x4006_1000 0xe000_0000 0x4006_0000 dmac 0x4003_f000 ext-bus i/f 0x4003_c000 reserved 0x4003_b000 rtc 0x4003_a000 watch counter 0x7000_0000 0x4003_9000 crc 0x4003_8000 mfs 0x6000_0000 0x4003_5000 lvd/ds mode 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4000_0000 0x4003_1000 int-req.read 0x4003_0000 exti 0x4002_f000 reserved 0x2400_0000 0x4002_e000 cr trim 0x2200_0000 0x4002_8000 0x4002_7000 a/dc 0x4002_6000 qprc 0x2008_0000 0x4002_5000 base timer 0x2000_0000 sram1 0x4002_4000 ppg 0x1ff8_0000 sram0 0x0020_8000 reserved 0x0020_0000 flash(work area) 0x4002_1000 0x0010_4000 reserved 0x4002_0000 mft unit0 0x0010_0000 security/cr trim 0x4001_6000 0x4001_5000 dual timer 0x4001_3000 0x4001_2000 sw wdt 0x0000_0000 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f reserved external device area reserved reserved cortex-m3 private peripherals 0x4004_0000 reserved 0x4003_6000 reserved reserved hdmi-cec/ remote control receiver 32mbytes bit band alias peripherals reserved 32mbytes bit band alias reserved reserved reserved see " l memory map (2)" for the memory size details. reserved reserved flash(main area) reserved document number: 002 - 05646 rev.*c page 74 of 147 mb9a150rb series 10.2 memory map (2) for more information about flash (main area)/flash (work area), see mb9ab40n/a40n/340n/140n/150r, mb9b520m/320m/120m series flash prog ramming manual . mb9af156mb/nb/rb mb9af155mb/nb/rb mb9af154mb/nb/rb 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_8000 0x2000_6000 0x2000_4000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_c000 0x1fff_a000 0x1fff_8000 0x0020_8000 0x0020_8000 0x0020_8000 sa7(8kb) sa7(8kb) sa7(8kb) sa6(8kb) sa6(8kb) sa6(8kb) sa5(8kb) sa5(8kb) sa5(8kb) 0x0020_0000 sa4(8kb) 0x0020_0000 sa4(8kb) 0x0020_0000 sa4(8kb) 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x0008_0000 0x0006_0000 0x0004_0000 sa3(8kb) sa3(8kb) sa3(8kb) 0x0000_0000 sa2(8kb) 0x0000_0000 sa2(8kb) 0x0000_0000 sa2(8kb) sa8(48kb) reserved flash(main area) 384 kbytes flash(main area) 256 kbytes flash(work area) 32 kbytes sa13(64kb) sa12(64kb) sa11(64kb) sa11(64kb) sa10(64kb) sa9(64kb) sa13(64kb) sa14(64kb) sa15(64kb) flash(work area) 32 kbytes flash(main area) 512 kbytes sa8(48kb) sa9(64kb) sa10(64kb) sa11(64kb) sa12(64kb) reserved reserved reserved sram0 32 kbytes reserved flash(work area) 32 kbytes reserved reserved reserved sa10(64kb) sa9(64kb) sa8(48kb) sram1 32 kbytes sram0 24 kbytes reserved reserved reserved sram1 24 kbytes reserved sram1 16 kbytes sram0 16 kbytes document number: 002 - 05646 rev.*c page 75 of 147 mb9a150rb series 10.3 peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_ 0 fff apb1 multi - function timer unit 0 0x4002_ 1 000 0x4002_ 3 fff reserved 0x4002_ 4 000 0x4002_ 4 fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff built - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt 0x4003_1000 0x4003_1fff interrupt source check register 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff hdmi - cec/remote control reception 0x4003_5000 0x4003_5 7 ff low - voltage detector 0x4003_5 800 0x4003_5 f ff deep standby mode controller 0x4003_6000 0x4003_ 7 fff reserved 0x4003_8000 0x4003_8fff multi - function serial 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_efff reserved 0x4003_f000 0x4003_ffff external bus interface 0x4004_0000 0x400 5 _ffff ahb reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_ 1 000 0x4 1ff _ f fff reserved document number: 002 - 05646 rev.*c page 76 of 147 mb9a150rb series 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the l level. ? initx=1 this is the period when the initx pin is the h level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to 0. ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to 1. ? input enabled indicates that the input function can be used. ? internal input fixed at 0 this is the status that the input function cannot be used. internal input is fixed at l. ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state . ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if t he pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. ? gpio selected in deep standby mode, pins switch to the general - purpos e i/o port. document number: 002 - 05646 rev.*c page 77 of 147 mb9a150rb series 11.1 list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 maintain previous state hi - z / internal input fixed at 0 maintain previous state main crystal oscillator output pin hi - z / internal input fixed at 0/ or input enable hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state/ when oscillation stops [1] , hi - z / internal input fixed at 0 maintain previous state/ when oscillatio n stops [1] , hi - z / internal input f ixed at 0 maintain previous state/ when oscillatio n stops [1] , hi - z / internal input fixed at 0 maintain previous state/ when oscillatio n stops [1] , hi - z / internal input fixed at 0 maintain previous state/ when oscillatio n stops [1] , hi - z / internal input fixed at 0 maintain previous state/ when oscillatio n stops [1] , hi - z / internal input fixed at 0 c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled document number: 002 - 05646 rev.*c page 78 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / input enabled gpio selected hi - z / input enabled gpio selected f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled document number: 002 - 05646 rev.*c page 79 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - g gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 maintain previous state hi - z/ internal input fixed at 0 maintain previous state sub crystal oscillator output pin hi - z / internal input fixed at 0/ or input enable hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state maintain previous state/when oscillation stops [2] , hi - z / internal input fixed at 0 maintain previous state/ when o scillation stops [2] , hi - z / internal input fixed at 0 maintain previous state/ when oscillation stops [2] , hi - z/ internal input fixed at 0 maintain previous state/when oscillation stops [2] , hi - z/ internal input fixed at 0 maintain previous state/ when osc illation stops [2] , hi - z/ internal input fixed at 0 h nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected document number: 002 - 05646 rev.*c page 80 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - i jtag selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state resource selected setting disabled setting disabled setting disabled hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected gpio selected j resource selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected gpio selected k external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected document number: 002 - 05646 rev.*c page 81 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - l analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / anal og input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at 0 / analog input enabled resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected gpio selected m analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / anal og input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected resource other than above selected hi - z / internal input fixed at 0 gpio selected document number: 002 - 05646 rev.*c page 82 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - n analog input selected hi - z hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 / analog input enabled trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected resource other than above selected hi - z / internal input fixed at 0 gpio selected o analog input selected hi - z hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled hi - z / internal input fixed at 0 /analog input enabled trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected external interrupt enabled selected maintain previous state resource other than above selected hi - z / internal input fixed at 0 gpio selected document number: 002 - 05646 rev.*c page 83 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - p analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 resource other than above selected hi - z / internal input fixed at 0 gpio selected document number: 002 - 05646 rev.*c page 84 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - q cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected r cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected document number: 002 - 05646 rev.*c page 85 of 147 mb9a150rb series pin status type function group power - on reset or low - voltage detectio n state initx input state device internal reset state run mode or sleep mode state t imer mode , rtc mode , or s top mode state deep standby r tc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - s wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected [1]. oscillation is stopped at sub timer mode, low - speed cr timer mode, rtc mode, stop mode, deep standby rtc mode, and deep standby stop mode. [2]. oscillation is stopped at stop mode and deep standby stop mode. document number: 002 - 05646 rev.*c page 86 of 147 mb9a150rb series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage [ 1 ] , [2] v cc v ss - 0.5 v ss + 4.6 v analog power supply voltage [ 1 ] , [3] av cc v ss - 0.5 v ss + 4.6 v analog reference voltage [ 1 ] , [3] avrh v ss - 0.5 v ss + 4.6 v input voltage [ 1 ] v i v ss - 0.5 v cc + 0.5 ( 4.6 v) v v ss - 0.5 v ss + 6.5 v 5 v tolerant analog pin input voltage [ 1 ] v ia v ss - 0.5 av cc + 0.5 ( 4.6 v) v output voltage [ 1 ] v o v ss - 0.5 v cc + 0.5 ( 4.6 v) v l level maximum output current [4] i ol - 10 ma l level average output current [5] i olav - 4 ma l level total maximum output current i ol - 100 ma l level total average output current [6] i olav - 50 ma h level maximum output current [4] i oh - - 10 ma h level average output current [5] i ohav - - 4 ma h level total maximum output current i oh - - 100 ma h level total average output current [6] i ohav - - 50 ma power consumption p d - 300 mw storage temperature t stg - 55 + 150 c [1]. these parameters are based on the condition that v ss = av ss = 0.0 v. [2]. v cc must not drop below v ss - 0.5 v. [3]. ensure that the voltage does not exceed v cc + 0. 5 v, for example, when the power is turned on. [4]. the maximum output current is defined as the v alue of the peak current flowing through any one of the corresponding pins. [5]. the average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. [6]. the total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. warning: semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.do not exceed any of these ratings. document number: 002 - 05646 rev.*c page 87 of 147 mb9a150rb series 12.2 recommended operating conditions (v ss = av ss = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc - 1.65 [2] 3.6 v analog power supply voltage av cc - 1.65 3.6 v av cc = v cc analog reference voltage avrh - 2.7 av cc v av cc 2.7 v av cc av cc v av cc < 2.7 v smoothing capacitor c s - 1 10 f for built - in regulator [ 1 ] operating t emperature t a - - 40 + 85 c [1]. see c pin in handling devices for the connection of the smoothing capacitor. [2]. in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruc tion execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconduct or device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than thes e conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet . if you are considering application under any c onditions other than listed herein, please contact sales representatives beforehand. document number: 002 - 05646 rev.*c page 88 of 147 mb9a150rb series 12.3 dc characteristics 12.3.1 current rating (v cc = av cc = 1.65 v to 3.6 v, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks typ [3] max [4] power supply current i cc vcc pll run mode cpu: 40 mhz, peripheral: 40 mhz 17.5 23.7 ma [ 1 ] , [5] cpu: 40 mhz, peripheral: the clock stops nop operation 8 11 ma [ 1 ] , [5] high - speed cr run mode cpu/ peripheral: 4 mhz [2] 1.9 3.1 ma [ 1 ] sub run mode cpu/ peripheral: 32 khz 120 810 a [ 1 ] , [6] low - speed cr run mode cpu/ peripheral: 100 khz 140 830 a [ 1 ] i ccs pll sleep mode peripheral: 40 mhz 11 15 ma [ 1 ] , [5] high - speed cr sleep mode peripheral: 4 mhz [ 2 ] 0.82 1.7 ma [ 1 ] sub sleep mode peripheral: 32 khz 105 800 a [ 1 ] , [6] low - speed cr sleep mode peripheral: 100 khz 125 810 a [ 1 ] [ 1 ]. when a l l ports are fixed. [ 2 ]. when setting it to 4 mhz by trimming. [ 3 ]. t a =+25c, v cc = 3.6 v [ 4 ]. t a =+ 85 c, v cc = 3.6 v [ 5 ]. when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) [ 6 ]. when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) document number: 002 - 05646 rev.*c page 89 of 147 mb9a150rb series parameter symbol pin name conditions value unit remarks typ [2] max [2] power supply current i cct vcc main timer mode t a = + 25 c , when lvd is off 2.0 2.7 ma [ 1 ] , [3] t a = + 85 c , when lvd is off - 3.2 ma [ 1 ] , [3] sub timer mode t a = + 25 c , when lvd is off 1 5 45 a [ 1 ] , [4} t a = + 85 c , when lvd is off - 440 a [ 1 ] , [4} i ccr rtc mode t a = + 25 c , when lvd is off 13 40 a [ 1 ] , [4] t a = + 85 c , when lvd is off - 380 a [ 1 ] , [4] i cch stop mode t a = + 25 c , when lvd is off 11 38 a [ 1 ] t a = + 85 c , when lvd is off - 370 a [ 1 ] i ccrd deep standby rtc mode t a = + 25 c , when lvd is off, when ram is off 2.0 12 a [ 1 ] , [4],[5] t a = + 25 c , when lvd is off, when ram is on 9.2 25 a [ 1 ] , [4],[5] t a = + 85 c , when lvd is off, when ram is off - 125 a [ 1 ] , [4],[5] t a = + 85 c , when lvd is off, when ram is on 195 a [ 1 ] , [4],[5] i cchd deep standby stop mode t a = + 25 c , when lvd is off, when ram is off 1.4 10 a [ 1 ] , [5] t a = + 25 c , when lvd is off, when ram is on 8.6 23 a [ 1 ] , [5] t a = + 85 c , when lvd is off, when ram is off - 120 a [ 1 ] , [5] t a = + 85 c , when lvd is off, when ram is on 190 a [ 1 ] , [5] [1]. when all ports are fixed. [2]. v cc =3.6 v [3]. when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit) [4]. when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit) [5]. ram on/off setting is on - chip sram only. document number: 002 - 05646 rev.*c page 90 of 147 mb9a150rb series 12.3.1.1 low - v oltage d etection current (v cc = 1.65 v to 3.6 v, v ss = 0v, t a = - 40c to + 85 c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cclvd vcc at operation for reset v cc = 3.6 v 0.13 0.3 a at not detect at operation for interrupt v cc = 3.6 v 0.13 0.3 a at not detect 12.3.1.2 flash memory current (v cc = 1.65 v to 3.6 v, v ss = 0v, t a = - 40c to + 85 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 9.5 11.2 ma [ 1 ] [1]. the current at which to write or erase flash memory, i ccflash is added to i cc . 12.3.1.3 a/d converter current (v cc = av cc = 1.65v to 3.6v, v ss = av ss = 0v, t a = - 40c to +85c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.27 0.42 ma at stop 0.03 10 a reference power supply current i ccavrh avrh at 1unit operation avrh=3.6 v 0.72 1.29 ma at stop 0.02 2.6 a document number: 002 - 05646 rev.*c page 91 of 147 mb9a150rb series 12.3.2 pin characteristics (v cc = av cc = 1.65v to 3.6v, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter sym bol pin name conditions value unit remarks min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0, md1 v cc 2.7 v v cc 0.8 - v cc + 0.3 v v cc < 2.7 v v cc 0.7 5v tolerant input pin v cc 2.7 v v cc 0.8 - v ss + 5.5 v v cc < 2.7 v v cc 0.7 l level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0, md1 v cc 2.7 v v ss - 0.3 - v cc 0.2 v v cc < 2.7 v v cc 0.3 5 v tolerant input pin v cc 2.7 v v ss - 0.3 - v cc 0.2 v v cc < 2.7 v v cc 0.3 h level output voltage v oh 4ma type v cc 2.7 v , i oh = - 4 ma v cc - 0.5 - v cc v v cc < 2.7 v , i oh = - 2 ma v cc - 0.45 l level output voltage v ol 4ma type v cc 2.7 v , i ol = 4 ma v ss - 0.4 v v cc < 2.7 v , i ol = 2 ma input leak current i il - - - 5 - + 5 a cec0_0, cec0_1, cec1_0, cec1_1 v cc = av cc = av rh = v ss = av ss = 0 .0 v - - +1.8 a pull - up resistor value r pu pull - up pin v cc 2.7 v 21 33 66 k v cc < 2.7 v - - 134 input capacitance c in other than vcc, vss, avcc, avss, avrh - - 5 15 pf document number: 002 - 05646 rev.*c page 92 of 147 mb9a150rb series 12.4 ac characteristics 12.4.1 main clock input characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0, x1 v cc 2.7 v 4 48 mhz when crystal oscillator is connected v cc < 2.7 v 4 20 - 4 48 mhz when using external clock input clock cycle t cylh - 20.83 250 ns when using external clock input clock pulse width - p wh /t cylh , p wl /t cylh 45 55 % when using external clock input clock rising time and falling time t cf, t cr - - 5 ns when using external clock internal operating c lock [1] frequency f cm - - - 40 mhz master clock f cc - - - 40 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock [2] f cp1 - - - 40 mhz apb1 bus clock [2] f cp 2 - - - 40 mhz apb2 bus clock [2] internal operating clock [1] cycle time t cycc - - 25 - ns base clock (hclk/fclk) t cycp0 - - 25 - ns apb0 bus clock [2] t cycp1 - - 25 - ns apb1 bus clock [2] t cycp2 - - 25 - ns apb2 bus clock [2] [1]. for more information about each internal operating clock, see chapter 2 - 1: clock in fm3 family peripheral manual . [2]. for about each apb bus which each peripheral is connected to, see block diagram in this data sheet. x0 document number: 002 - 05646 rev.*c page 93 of 147 mb9a150rb series 12.4.2 sub clock input characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a, x1a - - 32.768 - khz when crystal oscillator is connected [1] - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - p wh /t cyll , p wl /t cyll 45 - 55 % when using external clock [1]. for more information about crystal oscillator, see sub crystal oscillator in handling devices . x0 a document number: 002 - 05646 rev.*c page 94 of 147 mb9a150rb series 12.4.3 built - in cr oscillation characteristics 12.4.3.1 built - in high - speed cr (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbo l conditions value unit remarks min typ max clock frequency f crh t a = + 25 c ,v cc 2.7v 3.9 4 4 4.0 6 mhz when trimming [ 1 ] t a = - 20 c to + 85 c, v cc 2.7v 3.92 4 4.08 t a = - 40 c to + 85 c, v cc 2.7v 3.88 4 4.12 t a = + 25 c , v cc < 2.7v 3.9 4 4.1 t a = - 40 c to + 85 c v cc < 2.7v 3. 66 4 4. 20 t a = - 40 c to + 85 c 2.8 4 5.2 when not trimming frequency stabilization time t crwt - - - 30 s [ 2 ] [ 1 ]. in the case of using the values in cr trimming area of flash memory at shipment for frequency/t emperature trimming. [2]. this is the time to stabilize the frequency of high - speed cr clock after setting trimming value. this period is able to use high - spe ed cr clock as source clock. 12.4.3.2 built - in low - speed cr (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz document number: 002 - 05646 rev.*c page 95 of 147 mb9a150rb series 12.4.4 operating conditions of main pll 12.4.4.1 operating conditions of main pll (in the case of using main clock for input of main pll) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time [1] (lock up time) t lock 100 - - s pll input clock frequency f plli 4 - 16 mh z pll multiplication rate - 5 - 37 multiplier pll macro oscillation clock frequency f pllo 75 - 150 mh z main pll clock frequency [2] f clkpll - - 40 mh z [1]. time from when the pll starts operating until the oscillation stabilizes. [2]. for more information about main pll clock (clkpll), see chapter 2 - 1 : clock in fm3 family peripheral manual. 12.4.4.2 operating conditions of main pll (in the case of using the built - in high - speed cr for input clock of main pll ) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time [1] (lock up time) t lock 100 - - s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiplication rate - 19 - 35 multiplier pll macro oscillation clock frequency f pllo 72 - 150 mh z main pll clock frequency [2] f clkpll - - 40 mh z [1]. time from when the pll starts operating until the oscillation stabilizes. [2]. for more information about main pll clock (clkpll), see chapter 2 - 1 : clock in fm3 family peripheral manual. note: ? make sure to input to the main pll source clock, the high - speed cr clock (clkhc) that the frequency has been trimmed. ? when setting pll multiple rate, please take the accuracy of the built - in h igh - speed cr clock into account and prevent the master clock from exceeding the maximum frequency. k di vide r pllinput clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection main clock (clkmo) high - speed cr clock (clkhc) document number: 002 - 05646 rev.*c page 96 of 147 mb9a150rb series 12.4.5 reset input characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns 12.4.6 power - on reset timing (v ss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 1 - - ms *1 power ramp rate dv/dt vcc:0.2v to 2.70v 0.9 - 1000 mv/us *2 time until releasing power - on reset t prt - 0.446 - 0.744 ms *1: v cc must be held below 0.2v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of cold start (t off > 1 ms). note: ? if t off cannot be satisfied designs must assert external reset(initx) at power - up and at any brownout event per 1 2 . 4. 5. glossary vdh: detection voltage of low voltage detection reset. s ee 12.6 low - voltage detection characteristics v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 2 . 7 v document number: 002 - 05646 rev.*c page 97 of 147 mb9a150rb series 12.4.7 external bus timing 12.4.7.1 exte rnal bus clock output characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max out put frequency t cycle mclkout [1] v cc 2.7 v - 40 mhz v cc < 2.7 v - 20 mhz the external bus clock (mclkout) is a divided clock of hclk. for more information about setting of clock divider , see chapter 12 : external bus interface in fm3 family peripheral manual. . when external bus clock is not output, this characteristic does not give any effect on external bus operation. 12.4.7.2 external bus signal input/output characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v input signal output signal mclkout v ih v il v il v ih v oh v ol v ol v oh document number: 002 - 05646 rev.*c page 98 of 147 mb9a150rb series 12.4.7.3 separate bus access asynchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max moex min pulse width t oew moex v cc 2.7 v mclk n - 3 - ns v cc < 2.7 v mcsx address output delay time t csl C av mcsx[7:0], mad[24:0] v cc 2.7 v - 9 +9 ns v cc < 2.7 v - 12 +12 moex address hold time t oeh - ax moex, mad[24:0] v cc 2.7 v 0 mclk m+9 ns v cc < 2.7 v mclk m+12 mcsx moex delay time t cs l - oe l moex, mcsx[7:0] v cc 2.7 v mclk m - 9 mclk m+9 ns v cc < 2.7 v mclk m - 12 mclk m+12 moex mcsx time t oeh - c sh v cc 2.7 v 0 mclk m+9 ns v cc < 2.7 v mclk m+12 mcsx mdqm delay time t cs l - r dqml mcsx, mdqm[1:0] v cc 2.7 v mclk m - 9 mclk m+9 ns v cc < 2.7 v mclk m - 12 mclk m+12 data set up moex time t ds - oe moex, madata[15:0] v cc 2.7 v 20 - ns v cc < 2.7 v 38 - moex data hold time t dh - oe moex, madata[15:0] v cc 2.7 v 0 - ns v cc < 2.7 v m wex min pulse width t wew mwex v cc 2.7 v mclk n - 3 - ns v cc < 2.7 v mwex address output delay time t weh - ax mwex, mad[24:0] v cc 2.7 v 0 mclk m+9 ns v cc < 2.7 v mclk m+12 mcsx mwex delay time t csl - wel mwex, mcsx[7:0] v cc 2.7 v mclk n - 9 mclk n+9 ns v cc < 2.7 v mclk n - 12 mclk n+12 mwex mcsx delay time t weh - csh v cc 2.7 v 0 mclk m+9 ns v cc < 2.7 v mclk m+12 mcsx mdqm delay time t cs l - w dqml mcsx, mdqm[1:0] v cc 2.7 v mclk n - 9 mclk n+9 ns v cc < 2.7 v mclk n - 12 mclk n+12 mcsx data output time t cs l - dv mcsx, madata[15:0] v cc 2.7 v mclk - 9 mclk +9 ns v cc < 2.7 v mclk - 12 mclk +12 mwex data hold time t weh - dx mwex, madata[15:0] v cc 2.7 v 0 mclk m+9 ns v cc < 2.7 v mclk m+12 note: when the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16). document number: 002 - 05646 rev.*c page 99 of 147 mb9a150rb series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex document number: 002 - 05646 rev.*c page 100 of 147 mb9a150rb series 12.4.7.4 separate bus access synchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max address delay time t av mclk, mad[24:0] v cc 2.7 v 1 9 ns v cc < 2.7 v 12 mcsx delay time t csl mclk, mcsx[7:0] v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t cs h v cc 2.7 v 1 9 ns v cc < 2.7 v 12 moex delay time t rel mclk, moex v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t reh v cc 2.7 v 1 9 ns v cc < 2.7 v 12 data set up mclk time t ds mclk, madata[15:0] v cc 2.7 v 19 - ns v cc < 2.7 v 37 mclk data hold time t dh mclk, madata[15:0] v cc 2.7 v 0 - ns v cc < 2.7 v mwex delay time t wel mclk, mwex v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t we h v cc 2.7 v 1 9 ns v cc < 2.7 v 12 mdqm[1:0] delay time t dqml mclk, mdqm[1:0] v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t dqmh v cc 2.7 v 1 9 ns v cc < 2.7 v 12 mclk data output time t ods mclk, madata[15:0] v cc 2.7 v mclk+1 mclk+18 ns v cc < 2.7 v mclk+24 mclk data hold time t od mclk, madata[15:0] v cc 2.7 v 1 18 ns v cc < 2.7 v 24 note: ? when the external load capacitance c l = 30 pf. document number: 002 - 05646 rev.*c page 101 of 147 mb9a150rb series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s document number: 002 - 05646 rev.*c page 102 of 147 mb9a150rb series 12.4.7.5 multiplexed bus access asynchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max multiplexed a ddress delay time t a le - chmadv male, madata[15:0] v cc 2.7 v 0 +10 ns v cc < 2.7 v +20 multiplexed a ddress hold time t c hmadh v cc 2.7 v mclk n+0 mclk n+10 ns v cc < 2.7 v mclk n+0 mclk n+20 note: ? when the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16). mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0] document number: 002 - 05646 rev.*c page 103 of 147 mb9a150rb series 12.4.7.6 multiplexed bus access synchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk , ale v cc 2.7 v 1 9 ns v cc < 2.7 v 1 2 ns t chah v cc 2.7 v 1 9 ns v cc < 2.7 v 12 ns mclk multiplexed address delay time t chmadv m clk, madata[15:0] v cc 2.7 v 1 t od ns v cc < 2.7 v mclk multiplexed data output time t chmad x v cc 2.7 v 1 t od ns v cc < 2.7 v note: ? when the external load capacitance c l = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0] document number: 002 - 05646 rev.*c page 104 of 147 mb9a150rb series 12.4.7.7 nand flash memory mode (v cc = 1.65v to 3.6 v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit min max mnrex min pulse width t nrew mnrex v cc 2.7 v mclkn - 3 - ns v cc < 2.7 v data setup mnrextime t ds C nre mnrex, madata[15:0] v cc 2.7 v 20 - ns v cc < 2.7 v 38 - mnrex data hold time t dh C nre mnrex, madata[15:0] v cc 2.7 v 0 - ns v cc < 2.7 v mnale mnwex delay time t aleh - nwel mnale, mnwex v cc 2.7 v mclkm - 9 mclkm+9 ns v cc < 2.7 v mclkm - 12 mclkm+12 mnale mnwex delay time t alel - nwel mnale, mnwex v cc 2.7 v mclkm - 9 mclkm+9 ns v cc < 2.7 v mclkm - 12 mclkm+12 mncle mnwex delay time t cleh - nwel mncle, mnwex v cc 2.7 v mclkm - 9 mclkm+9 ns v cc < 2.7 v mclkm - 12 mclkm+12 mnwex mncle delay time t nweh - clel mncle, mnwex v cc 2.7 v 0 mclkm+9 ns v cc < 2.7 v mclkm+12 mnwex min pulse width t nwew mnwex v cc 2.7 v mclkn - 3 - ns v cc < 2.7 v mnwex data output time t nwel C dv mnwex, madata[15:0] v cc 2.7 v - 9 + 9 ns v cc < 2.7 v - 12 +12 mnwex data hold time t nweh C dx mnwex, madata[15:0] v cc 2.7 v 0 mclkm+9 ns v cc < 2.7 v mclkm+12 note: ? when the external load capacitance c l = 30 pf (m=0 to 15, n=1 to 16). document number: 002 - 05646 rev.*c page 105 of 147 mb9a150rb series figure 1 . nand flash memory read figure 2 . nand flash memory address write mclk mnrex madata [ 15 : 0 ] read mclk mnale mncle madata [ 15 : 0 ] mnwex write document number: 002 - 05646 rev.*c page 106 of 147 mb9a150rb series figure 3 . nand flash memory command write mclk mnale mncle madata [ 15 : 0 ] mnwex write document number: 002 - 05646 rev.*c page 107 of 147 mb9a150rb series 12.4.7.8 external ready input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max mclk mrdy input setup time t rdyi mclk, mrdy v cc 2.7 v 19 - ns v cc < 2.7 v 37 when rdy is input when rdy is released mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycles t rdyi 2 cycles t rdyi 0.5vcc document number: 002 - 05646 rev.*c page 108 of 147 mb9a150rb series 12.4.8 base timer input timing 12.4.8.1 timer input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck, tin) - 2 t cycp - ns 12.4.8.2 trigger input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note : ? t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is connected to, see block diagram in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l document number: 002 - 05646 rev.*c page 109 of 147 mb9a150rb series 12.4.9 csio/uart timing 12.4.9.1 csio (spi = 0, scinv = 0) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sck x master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 30 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , sotx - 50 - 30 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see block diagram in this data shee t. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. document number: 002 - 05646 rev.*c page 110 of 147 mb9a150rb series master mode slave mode t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi sck sot sin t slsh t shsl v ih t f t r v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe sck sot sin document number: 002 - 05646 rev.*c page 111 of 147 mb9a150rb series 12.4.9.2 csio (spi = 0, scinv = 1) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 30 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , sotx - 50 - 30 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx _1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. document number: 002 - 05646 rev.*c page 112 of 147 mb9a150rb series master mode slave mode t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove document number: 002 - 05646 rev.*c page 113 of 147 mb9a150rb series 12.4.9.3 csio (spi = 1, scinv = 0) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 30 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns sot sck delay time t sovli sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , s ot x - 50 - 30 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time.about the apb bus number which multi - function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacit ance c l = 30 pf. document number: 002 - 05646 rev.*c page 114 of 147 mb9a150rb series master mode slave mode *: changes when writing to tdr register t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi sck sot sin t f t r t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe sck sot sin document number: 002 - 05646 rev.*c page 115 of 147 mb9a150rb series 12.4.9.4 csio (spi = 1, scinv = 1) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 30 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns sot sck delay time t sovhi sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , s ot x - 50 - 30 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacit ance c l = 30 pf. document number: 002 - 05646 rev.*c page 116 of 147 mb9a150rb series master mode slave mode 12.4.9.5 uart external clock input (ext = 1) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min max serial clock l pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock h pulse width t shsl t cycp + 10 - ns sck falling time t f - 5 ns sck rising time t r - 5 ns t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t shsl v i l v i l v i l v ih v ih v ih t r t f t slsh s ck document number: 002 - 05646 rev.*c page 117 of 147 mb9a150rb series 12.4.10 external input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name condition s value unit remarks min ma x input pulse width t inh, t inl adtg - 2 t cycp [1] - ns a/d converter trigger input frckx free - run timer input clock icxx input capture dtixx waveform generator intxx, nmix [2] 2 t cycp + 100 [1] - ns external interrupt, nmi [3] 500 - ns wkupx [4] 600 - ns deep standby wake up [ 1 ]. t cycp indicates the apb bus clock cycle time. about the apb bus number which the multi - function timer is connected to , see block diagram in this data sheet. [ 2 ]. when in run mode, in sleep mode. [ 3 ]. when in stop mode, in timer mode. [ 4 ]. when in deep standby rtc mode, in deep standby stop mode. document number: 002 - 05646 rev.*c page 118 of 147 mb9a150rb series 12.4.11 quadrature position/revolution counter timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit min max ain pin h width t ahl - 2 t cycp [1] - ns ain pin l width t all - bin pin h width t bhl - bin pin l width t bll - bin rising time from ain pin h level t aubu pc_mode2 or pc_mode3 ain falling time from bin pin h level t buad pc_mode2 or pc_mode3 bin falling time from ain pin l level t adbd pc_mode2 or pc_mode3 ain rising time from t bdau pc_mode2 or pc_mode3 ain rising time from bin pin h level t buau pc_mode2 or pc_mode3 bin falling time from ain pin h level t aubd pc_mode2 or pc_mode3 ain falling time from bin pin l level t bdad pc_mode2 or pc_mode3 bin rising time from ain pin l level t adbu pc_mode2 or pc_mode3 zin pin h width t zhl qcr:cgsc=0 zin pin l width t zll qcr:cgsc=0 ain/bin rising and falling time from determined zin level t zabe qcr:cgsc=1 determined zin level from ain/bin rising and falling time t abez qcr:cgsc=1 [1]. t cycp indicates the apb bus clock cycle time.about the apb bus number which the quadrature position/revolution counter is connected to, see block diagram i n this data sheet. document number: 002 - 05646 rev.*c page 119 of 147 mb9a150rb series ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain document number: 002 - 05646 rev.*c page 120 of 147 mb9a150rb series zin zin ain/bin document number: 002 - 05646 rev.*c page 121 of 147 mb9a150rb series 12.4.12 i 2 c timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (v p /i ol ) [ 1 ] 0 100 0 400 khz (repeated) start condition hold time sda scl t hdsta 4.0 - 0.6 - s scl clock l width t low 4.7 - 1.3 - s scl clock h width t high 4.0 - 0.6 - s (repeated) start condition setup time scl sda t susta 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45 [ 2] 0 0.9 [ 3] s data setup time sda scl t sudat 250 - 100 - ns stop condition setup time scl sda t susto 4.0 - 0.6 - s bus free time between stop condition and start condition t buf 4.7 - 1.3 - s noise filter t sp - 2 t cycp [ 4] - 2 t cycp [ 4] - ns [1]. r and c l represent the pull - up resistor and load capacitance of the scl and sda lines, respectively. v p indicates the power supply voltage of the pull - up resistor and i ol indicates v ol guaranteed current. [2]. the maximum t hddat must satisfy that it does n o t extend at least l period (t low ) of device's scl signal. [3]. a fast - mode i 2 c bus device can be used on a s tandard - mode i 2 c bus system as long as the device satisfies the requirement of t sudat 250 ns. [4]. t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is connected to, see block diagram in this data sheet. to use s tandard - mode, set the apb bus clock at 2 mhz or more.to use fast - mode, set the apb bus clock at 8 mhz or more. sda s cl document number: 002 - 05646 rev.*c page 122 of 147 mb9a150rb series 12.4.13 etm timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk, traced[3:0] v cc 2.7v 2 11 ns v cc < 2.7v 2 15 traceclk frequency 1/ t trace traceclk v cc 2.7v - 40 mhz v cc < 2.7v - 20 mhz traceclk clock cycle t trace v cc 2.7v 25 - ns v cc < 2.7v 50 - ns note: ? when the external load capacitance c l = 30 pf. hclk traceclk traced[3:0] document number: 002 - 05646 rev.*c page 123 of 147 mb9a150rb series 12.4.14 jtag timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max tms, tdi setup time t jtags tck, tms, tdi v cc 2.7v 15 - ns v cc < 2.7v tms, tdi hold time t jtagh tck, tms, tdi v cc 2.7v 15 - ns v cc < 2.7v tdo delay time t jtagd tck, tdo v cc 2.7v - 25 ns v cc < 2.7v - 45 note: ? when the external load capacitance c l = 30 pf. tck tms/tdi tdo document number: 002 - 05646 rev.*c page 124 of 147 mb9a150rb series 12.5 12 - bit a/d converter 12.5.1 electrical c haracteristics for the a/d converter (v cc = av cc = 1.65v to 3.6v, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 2.4 4.5 lsb differential nonlinearity - - - 2.3 2.5 lsb zero transition voltage v zt anxx - 7 15 mv full - scale transition voltage v fst anxx - avrh 7 avrh 15 mv conversion time [ 1 ] - - 2.0 - - s av cc 2.7 v 4.0 - - 1.8 v < av cc < 2.7 v 10 - - 1.65 v < av cc < 1.8 v sampling time [2] t s - 0.6 - 10 us av cc 2.7 v 1.2 - 1.8 v < av cc < 2.7 v 3.0 - 1.65 v < av cc < 1.8 v compare clock cycle [3] t cck - 100 - 1000 ns av cc 2.7 v 200 1.8 v < av cc < 2.7 v 500 1.65 v < av cc < 1.8 v state transition time to operation permission t stt - - - 1.0 s analog input capacity c ain - - - 9.4 pf analog input resistor r ain - - - 2.2 k av cc 2.7 v 5.5 1.8 v < av cc < 2.7 v 10.5 1.65 v < av cc < 1.8 v interchannel disparity - - - - 4 lsb analog port input leak current - anxx - - 5 a analog input voltage - anxx av ss - avrh v reference voltage - avrh 2.7 - av cc v av cc 2.7 v av cc av cc < 2.7 v [ 1 ]. the conversion time is the value of sampling time (t s ) + compare time (t c ). the condition of the minimum conversion time is the following. av cc 2.7 v, hclk= 40 mhz sampling time: 0.6 s , compare time: 1.4 s 1.8 v < av cc < 2.7 v , hclk= 40 mhz sampling time: 1.2 s, compare time: 2.8 s 1.65 v < av cc < 1.8 v , hclk= 40 mhz sampling time: 3 s, compare time: 7 s e nsure that it satisfies the value of the sampling time (t s ) and compare clock cycle (t cck ). for setting of the sampling time and compare clock cycle, see chapter 1 - 1 : a/d converter in fm3 family peripheral manual. analog macro part. the register setting s of the a / d c onverter are reflected in the operation according to the apb bus clock timing. for the number of the apb bus to which the a/d converter is connected, see block diagram . the base clock (hclk) is used to generate the sampling time and the compare clock cycle. [ 2 ]. a necessary sampling time changes by external impedance. ensure that it sets the sampling time to satisfy ( equation 1 ). [ 3 ]. the compare tim e ( t c ) is the value of ( equation 2). document number: 002 - 05646 rev.*c page 125 of 147 mb9a150rb series (equation 1) t s ( r ain + r ext ) c ain 9 t s : sampling time[ns] r ain : input resistor of a/d[k ] = 2.2 k at 2.7 v < av cc < 3.6 v input resistor of a/d[k ] = 5.5 k at 1.8 v < av cc < 2.7 v input resistor of a/d[k ] = 10.5 k at 1.65 v < av cc < 1.8 v c ain : input capacity of a/d[pf] = 9.4 pf at 1.65 v < av cc < 3.6 v r ext : output impedance of external circuit[k ] (equation 2 ) t c = t cck 14 t c : compare time t cck : compare clock cycle r ext r ain c ain analog signal source an xx analog input pin c omparator document number: 002 - 05646 rev.*c page 126 of 147 mb9a150rb series 12.5.2 definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonlinearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential nonlinearity : deviation fr om the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v zt 4094 n: a/d converter digital output value. v zt : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonlinearity differential nonlinearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t document number: 002 - 05646 rev.*c page 127 of 147 mb9a150rb series 12.6 low - v oltage d etection c haracteristics 12.6.1 low - v oltage d etection r eset (t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr [ 1 ] = 00000 1.38 1.50 1.6 0 v when voltage drops released voltage vdh 1.43 1.55 1.65 v when voltage rises detected voltage vdl svhr [ 1 ] = 00001 1.43 1.55 1.65 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 00010 1.47 1.60 1.73 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 00011 1.52 1.65 1.78 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 00100 1.56 1.70 1.84 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 00101 1.61 1.75 1.89 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 00110 1.66 1.80 1.94 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 00111 1.70 1.85 2.00 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01000 1.75 1.90 2.05 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01001 1.79 1.95 2.11 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01010 1.84 2.00 2.16 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01011 1.89 2.05 2.21 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01100 2.30 2.50 2.70 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01101 2.39 2.60 2.81 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01110 2.48 2.70 2.92 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 01111 2.58 2.80 3.02 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises document number: 002 - 05646 rev.*c page 128 of 147 mb9a150rb series parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr [ 1 ] = 10000 2.67 2.90 3.13 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 10001 2.76 3.00 3.24 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 10010 2.85 3.10 3.35 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [ 1 ] = 10011 2.94 3.20 3.46 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises lvd stabilization wait time t lvdw - - - 5200 t cycp [2] s lvd detection delay time t lvddl - - - 200 s [ 1 ]. the svhr bit of low - v oltage detection voltage control register (lvd_ctl) is initialized to 00000 by l ow - v oltage d etection r ese t . [ 2 ]. t cycp indicates the apb2 bus clock cycle time. document number: 002 - 05646 rev.*c page 129 of 147 mb9a150rb series 12.6.2 interrupt of l ow - v oltage d etection (t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 00100 1.56 1.70 1.84 v when voltage drops released voltage vdh 1.61 1.75 1.89 v when voltage rises detected voltage vdl svhi = 00101 1.61 1.75 1.89 v when voltage drops released voltage vdh 1.66 1.80 1.94 v when voltage rises detected voltage vdl svhi = 00110 1.66 1.80 1.94 v when voltage drops released voltage vdh 1.70 1.85 2.00 v when voltage rises detected voltage vdl svhi = 00111 1.70 1.85 2.00 v when voltage drops released voltage vdh 1.75 1.90 2.05 v when voltage rises detected voltage vdl svhi = 01000 1.75 1.90 2.05 v when voltage drops released voltage vdh 1.79 1.95 2.11 v when voltage rises detected voltage vdl svhi = 01001 1.79 1.95 2.11 v when voltage drops released voltage vdh 1.84 2.00 2.16 v when voltage rises detected voltage vdl svhi = 01010 1.84 2.00 2.16 v when voltage drops released voltage vdh 1.89 2.05 2.21 v when voltage rises detected voltage vdl svhi = 01011 1.89 2.05 2.21 v when voltage drops released voltage vdh 1.93 2.10 2.27 v when voltage rises detected voltage vdl svhi = 01100 2.30 2.50 2.70 v when voltage drops released voltage vdh 2.39 2.60 2.81 v when voltage rises detected voltage vdl svhi = 01101 2.39 2.60 2.81 v when voltage drops released voltage vdh 2.48 2.70 2.92 v when voltage rises detected voltage vdl svhi = 01110 2.48 2.70 2.92 v when voltage drops released voltage vdh 2.58 2.80 3.02 v when voltage rises detected voltage vdl svhi = 01111 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 10000 2.67 2.90 3.13 v when voltage drops released voltage vdh 2.76 3.00 3.24 v when voltage rises detected voltage vdl svhi = 10001 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 10010 2.85 3.10 3.35 v when voltage drops released voltage vdh 2.94 3.20 3.46 v when voltage rises detected voltage vdl svhi = 10011 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises lvd stabilization wait time t lvdw - - - 5200 t cycp [1] s lvd detection delay time t lvddl - - - 200 s [1]. t cycp indicates the apb2 bus clock cycle time. document number: 002 - 05646 rev.*c page 130 of 147 mb9a150rb series 12.7 flash memory write/erase characteristics 12.7.1 write / erase time ( v cc = 1.65v to 3.6v , t a = - 40 c to + 85 c ) parameter value unit remarks typ [1] max [1] sector erase time large sector 1.1 2.7 s includ es write time prior to internal erase small sector 0.3 0.9 half word (16 - bit) write time 30 528 s not including system - level overhead time chip erase time 11.2 30.5 s includes write time prior to internal erase [1].the typical value is immediately after shipment , the maximam value is guarantee value under 100,000 cycle of erase/write. 12.7.2 write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1,000 20 [1] 10,000 10* [1]. at average + 85 c document number: 002 - 05646 rev.*c page 131 of 147 mb9a150rb series 12.8 return time from low - power consumption mode 12.8.1 return f actor: interrupt/wkup the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. 12.8.1.1 return c ount t ime ( v cc = 1.65 v to 3.6 v, v ss = 0v, t a = - 40c to + 85 c ) parameter symbol value unit remarks typ max [1] sleep mode t icnt t cycc s high - speed cr timer mode, main timer mode, pll timer mode 40 80 s low - speed cr timer mode 350 700 s sub timer mode 690 880 s rtc mode, stop mode 278 523 s deep standby rtc mode deep standby stop mode 318 603 s when ram is off 278 523 s when ram is on [1]. the maximum value depends on the accuracy of built - in cr. 12.8.1.2 operation example of return from l ow - p ower consumption mode (by external interrupt [1] ) [1]. external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u document number: 002 - 05646 rev.*c page 132 of 147 mb9a150rb series 12.8.1.3 operation example of return from low - power consumption mode (by internal resource interrupt [1] ) [1]. internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see c hapter 6 : low power consumption mode and operations of standby modes in fm3 family p eripheral m anual . ? when interrupt recoveries, the operation mode that cpu recoveries depend on the state before the low - power consumption mode transition. see c hapter 6 : low power consumption mode in fm3 family p eripheral m anual . i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u document number: 002 - 05646 rev.*c page 133 of 147 mb9a150rb series 12.8.2 return f actor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. 12.8.2.1 return c ount t ime ( v cc = 1.65 v to 3.6 v, v ss = 0v, t a = - 40c to + 85 c ) parameter symbol value unit remarks typ max [1] sleep mode t rcnt 148 263 s high - speed cr timer mode, main timer mode, pll timer mode 148 263 s low - speed cr timer mode 258 483 s sub timer mode 322 516 s rtc/stop mode 278 523 s deep standby rtc mode deep standby stop mode 318 603 s when ram is off 278 523 s when ram is on [1]. the maximum value depends on the accuracy of built - in cr. 12.8.2.2 operation example of return from l ow - p ower consumption mode (by initx) i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e document number: 002 - 05646 rev.*c page 134 of 147 mb9a150rb series 12.8.2.3 operation example of return from low power consumption mode (by internal resource reset [1] ) [1]. internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see c hapter 6 : low power consumption mode and operations of standby modes in fm3 family p eripheral m anual ? when interrupt recoveries, the operation mode t hat cpu recoveries depend on the state before the low - power consumption mode transition. see c hapter 6 : low power consumption mode in fm3 family p eripheral m anual ? the time during the power - on reset/low - voltage detection reset is excluded. see 12.4 .6 power - on reset timing in 12.4 ac characteristics in electrical characteristics for the detail on the time during the power - on reset/low - voltage detect ion reset. ? when in recovery from reset, cpu changes to the h igh - speed cr r un mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the m ain pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e document number: 002 - 05646 rev.*c page 135 of 147 mb9a150rb series 13. ordering information part number on - chip flas h memory on - chip sram package packing mb9af 154 m b pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte plastic ? lqfp 80 - pin (0.5 mm pitch) , (lqh080) tray mb9af 155 m b pmc - g - jne2 main: 384 kbyte work: 32 kbyte 48 kbyte mb9af 156 m b pmc - g - jne2 main: 512 kbyte work: 32 kbyte 64 kbyte mb9af 154 m b bgl - ge1 main: 256 kbyte work: 32 kbyte 32 kbyte plastic ? pfbga 96 - pin (0.5 mm pitch) , (fdg096) mb9af 155 m b bgl - ge1 main: 384 kbyte work: 32 kbyte 48 kbyte mb9af 156 m b bgl - ge1 main: 512 kbyte work: 32 kbyte 64 kbyte mb9af 154 n b pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte plastic ? lqfp 1 00 - pin (0.5 mm pitch) , (lqi100) mb9af 155 n b pmc - g - jne2 main: 384 kbyte work: 32 kbyte 48 kbyte mb9af 156 n b pmc - g - jne2 main: 512 kbyte work: 32 kbyte 64 kbyte mb9af 154 n b bgl - ge1 main: 256 kbyte work: 32 kbyte 32 kbyte plastic ? pfbga 1 12 - pin (0. 8 mm pitch) , ( lbc112 ) mb9af 155 n b bgl - ge1 main: 384 kbyte work: 32 kbyte 48 kbyte mb9af 156 n b bgl - ge1 main: 512 kbyte work: 32 kbyte 64 kbyte mb9af 154rbpmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte plastic ? lqfp 1 20 - pin (0. 5 mm pitch) , ( lqm120 ) mb9af 155rbpmc - g - jne2 main: 384 kbyte work: 32 kbyte 48 kbyte mb9af 156rbpmc - g - jne2 main: 512 kbyte work: 32 kbyte 64 kbyte document number: 002 - 05646 rev.*c page 136 of 147 mb9a150rb series 14. package dimensions package type package code lqfp 120 lqm120 002 - 16172 ** m i n . n o m . m ax . 0 7 . 1 a a 1 0 . 0 5 0 . 1 5 b 0 .1 7 0 .2 2 0 .2 7 c 0 . 1 1 5 0 . 1 9 5 d 1 8 . 0 0 b s c d 1 1 6 . 0 0 b s c e 0 . 5 0 bs c e e 1 l 0 .4 5 0 .6 0 0 .7 5 1 8 . 0 0 b s c 1 6 . 0 0 b s c d i m e n s io n s s y m b o l 0 8 s i d e vie w b o tt o m vie w t o p v i e w 1 120 d 1 d e e e 1 0.20 c a - b d 0.10 c a - b d 0.08 c a - b d b 0.08 c s eati n g pla n e a a' a a 1 0.25 1 0 l b s ec t i on a - a' c 9 4 5 7 3 4 5 7 3 8 7 5 2 2 6 30 31 60 61 90 91 1 30 31 60 0 9 1 6 91 package ou t line, 1 20 le a d l q f p 18 . 0x18 . 0x1 . 7 m m lq m 120 r ev * * document number: 002 - 05646 rev.*c page 137 of 147 mb9a150rb series package type package code lqfp 100 lqi100 002 - 11500 *a n o t e s : 1 . a ll d i m e n s io n s a r e i n m i ll i m e t e r s . 2. d a t u m pla n e h i s lo c a t e d a t t h e bot t o m of t h e mold partin g li n e coi n c i d e n t w i t h w h e r e t h e l e a d e x i t s t h e body . 3 . d a tums a - b a n d d t o b e d e t e rmi n e d a t d a t u m p l a n e h . 4. to b e d e t e r m i n e d a t s e a t i n g plane c . 5 . d i m e n sio n s d1 a nd e 1 d o n ot i nc l ud e m ol d p r o t ru si o n . allowable protrusi o n is 0 . 25 mm p r e si d e . d i m e n s i o n s d 1 a n d e 1 i n c l u d e m o l d m i s m a t c h a n d a r e d e t e rmine d a t d a t u m plane h . 6 . d e t a i l s o f p i n 1 i d e n t i f i e r a r e o p t i o n a l b u t m u s t be l o c ate d w i t h i n th e zo n e i n d i c a t e d . 7 . r e g a r d l e s s of t h e r e l a t i v e s i z e o f t h e u p p e r a n d l o w e r b o d y s e c t i o n s . d i m e n s i o n s d 1 a n d e 1 a r e d e t e r m i n e d a t t h e larges t f e a t u r e o f t h e b o d y e x c l u s i v e o f m o l d f l a s h a n d g a te burrs . b u t i n clu d i n g a n y m i s m a t c h b e t w e e n t h e u p p e r a nd lowe r s e c t ion s of t h e mol d e r b o dy . 8 . d i m e n s i o n b d o e s n o t i n c l u d e d a m b a r p r o t r u s i o n . t h e d a mba r p r o t r u s i o n ( s ) s h a l l n o t c a u s e t h e l e a d w i d t h to e x c e e d b m a x i m u m b y m o r e t h a n 0 . 0 8 m m . d a m b a r c a n n o t b e l o cated o n t h e l o w e r r a d i u s o r t h e l e a d f oot . 9. t h e s e d i m e n s ion s a p p l y t o t h e fla t s e c t i o n of the lea d b e t w e e n 0 . 10m m a n d 0.25 m m f r o m t h e lead tip . 10 . a 1 i s d e f i n e d a s t h e d i s t a n c e f r om t h e s e a t i n g p l a n e t o t h e low e s t p o i n t of t h e p a c k age body . d im e n s io n s symbol m in . n o m . max . a 1.7 0 a1 0.0 5 0.1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 6 . 00 bsc d 1 1 4 .00 bs c e 0 . 50 bsc e e1 l 0 .4 5 0 .6 0 0 .7 5 l1 0.3 0 0.5 0 0.7 0 1 6. 00 bsc 1 4. 00 bsc a a 1 0.25 0.0 8 c 1 100 d 1 d e 1 e e 4 4 0.0 8 c a - b d 7 5 seat i n g pla n e 0.2 0 c a - b d 0.1 0 c a - b d b se c t io n a-a ' c 9 a a ' 5 7 5 7 3 3 6 8 1 0 2 2 l1 l b d 1 d e 1 e 4 4 5 7 5 7 25 26 50 51 75 76 side v i ew top v i ew b o tt o m vie w d e t a il a 1 25 26 50 5 7 1 5 100 76 package ou t line, 1 00 le a d l q f p 14.0x14.0x1.7 mm lq i 100 r ev * a document number: 002 - 05646 rev.*c page 138 of 147 mb9a150rb series package type package code lqfp 80 lqh080 002 - 11501 ** d i men s io n s m i n . n o m . m ax . 0 7 . 1 a a 1 0 . 0 5 0 . 1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 4 . 0 0 b s c . d 1 12.00 b s c . e 0 . 5 0 bs c e e 1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 0 . 3 0 0 . 5 0 0 . 7 0 1 4 . 0 0 b s c . 1 2 . 0 0 b s c . s y m b o l b o t t o m vie w a a 1 0 . 2 5 1 8 0 d 1 d e b d 0. 2 0 c a - b d 0. 1 0 c a - b d 0. 0 8 c a - b d e e 1 4 5 7 3 4 5 7 3 8 7 5 2 1 0 b s e c t i o n a - a ' c 9 2 s ea t i n g p l an e 0. 0 8 c a a ' 6 l 1 l s i de vie w t o p vie w 2 0 2 1 4 0 1 4 0 6 6 1 0 6 1 4 8 0 6 1 2 1 4 0 1 2 0 package ou t line, 80 le a d lq f p 12.0x12.0x1.7 mm lq h 080 r e v * * document number: 002 - 05646 rev.*c page 139 of 147 mb9a150rb series package type package code bga 112 lbc112 002 - 13225 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 3 5 0 . 0 0 0 . 8 0 bs c 0 . 8 0 bs c 0 . 4 5 11 2 1 1 0 . 5 5 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 2 5 m i n . - 8 . 0 0 bs c 8 . 0 0 bs c 1 1 1 0 . 0 0 bs c 1 0 . 0 0 bs c n o m . - 1 . 4 5 0 . 4 5 m ax . s e 0 . 0 0 0 . 3 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0 . 20 c 2 x b 0 . 20 c 2 x i n d e x ma rk pin a 1 c o rne r 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 11 2 x b 0 . 08 c a b 5 6 6 s i d e vie w 0 . 10 c c d e t a il a b o tt o m vie w t o p vie w d e t a i l a 10 . 00x10 . 00 x1.45 mm l b c 112 r ev * * package ou t line, 11 2 ball f b g a document number: 002 - 05646 rev.*c page 140 of 147 mb9a150rb series package type package code bga 96 fdg096 002 - 13224 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 2 0 0 . 0 0 0 . 5 0 bs c 0 . 5 0 bs c 0 . 3 0 9 6 1 1 0 . 4 0 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 1 5 m i n . - 5 . 0 0 bs c 5 . 0 0 bs c 1 1 6 . 0 0 bs c 6 . 0 0 bs c n o m . - 1 . 3 0 0 . 3 5 m ax . s e 0 . 0 0 0 . 2 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0.2 0 c 2 x b 0.2 0 c 2 x i n d e x m a r k p i n a 1 corner 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 96 x b 0.0 5 c a b 5 6 6 s i de vie w 0.2 0 c 0.0 8 c c deta i l a b o t t o m vie w t o p vie w deta i l a 6.0x6.0x1.3 m m f d g 096 r ev * * package ou t line, 9 6 ball f bga document number: 002 - 05646 rev.*c page 141 of 147 mb9a150rb series 15. errata this chapter describes the errata for mb9b150r series . details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. contact your local cypress sales representative if you have questions. 15.1 part numbers affected part number initial revision mb9af154rpmc - g - jne2, mb9af155rpmc - g - jne2, mb9af156rpmc - g - jne2, mb9af154npmc - g - jne2, mb9af155npmc - g - jne2, mb9af156npmc - g - jne2, mb9af154nbgl - ge1, mb9af155nbgl - ge1, mb9af156nbgl - ge1, mb9af154mpmc - g - jne2, mb9af155mpmc - g - jne2, mb9af156mpmc - g - jne2, mb9af154mbgl - ge1, mb9af155mbgl - ge1 , mb9af156mbgl - ge1 rev. a mb9af154rapmc - g - jne2, mb9af155rapmc - g - jne2, mb9af156rapmc - g - jne2, mb9af154napmc - g - jne2, mb9af155napmc - g - jne2, mb9af156napmc - g - jne2, mb9af154nabgl - ge1, mb9af155nabgl - ge1, mb9af156nabgl - ge1, mb9af154mapmc - g - jne2, mb9af155mapmc - g - jne2, mb9af156mapmc - g - jne2, mb9af154mabgl - ge1, mb9af155mabgl - ge1, mb9af156mabgl - ge1 15.2 qualification status product status: in production ? qual. 15.3 errata summary this table defines the errata applicability to available devices. items p art number silicon revision fix status [ 1 ] hdmi - cec a rbitration l ost issue refer to 15.1 initial rev. fixed in rev. a [ 2 ] hdmi - cec polling message is sue refer to 15.1 initial rev., rev. a fixed in rev. b 1. hdmi - cec arbitration lost issue ? problem definition large external load on cec bus may cause arbitration lost. ? parameters affected n/a ? trigger condition(s) the arbitration lost detection mechanism samples outputting signals and determin e s that arbitration lost occurs if sampled signals do not match the outputting signals. the large external load on the cec bus increases slew rate of the signals. the increased slew document number: 002 - 05646 rev.*c page 142 of 147 mb9a150rb series rate makes the mismatch between outputting signals and sampled signals and the mismatch misleads mcu that arbitration lost occurs. ? scope of impact once the arbitration lost is detec ted, the cec aborts the transmission. any transmission cannot be completed. ? workaround this error cannot be avoided by any software. reduce the external load. ? fix status this issue was fixed in rev. a. 2. hdmi - cec polling message issue ? problem definition e rror#1) while mcu sends a polling message, it always returns a nack to a message coming to the mcu from another node. error#2) mcu always waits for 7 - bit signal free on cec line before it drives the line even when the last line initiator was another node. ? parameters affected n/a ? trigger condition(s) this error always happens. ? scope of impact mcu does not reply properly to another node. ? workaround the software workaround is applied to error #1. 1. store 0x0 to sfree register. 2. monitor cec line with gpio and wait until high on the cec line lasts for the signal free time. 3. store frame data to txdata register and store 0x0f to rcadr1 or rcadr2 register. it sends a message after 3~4 clocks of 32.768 khz clock when txdata is stored. if the device receives a frame from another node within 2~3 clocks after storing txdata, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after storing txdata, the arbitration lost occurs. in these cases: 4 - a - 1 . set rcadr1 or rcadr2 to former value from 0x0f to reply ack 4 - a - 2. return back to step 2 above if the device receives a frame from another node within 1~2 clocks after storing txdata, take these steps. 4 - b - 1. monitor cec line with gpio after 50us from storing txdata 4 - b - 2. set txen to 1 - > 0 - > 1 immediately when gpio finds low on the cec line 4 - b - 3. set rcadr1 or rcadr2 to former value from 0x0f to reply ack 4 - b - 4. return back to step 2 above for error #2, there is no software workaround, but signal free time of fixed 7 - bit does not violate hdmi - cec specification. the specification says signal free time must be more than and equals to 5 - bit. ? fix status ? this issue was fixed in rev. b . document number: 002 - 05646 rev.*c page 143 of 147 mb9a150rb series 16. major changes spansion publication number: mb9a150rb_ds706 - 00047 page section change results revision 0.1 - - initial release revision 1.0 - - preliminary data sheet 1 features on - chip memories corrected the description of "flash memory". 7 1. product lineup 1.2. function corrected the value of channel number of the "base timer". 71 7.handling devices ? added the description of "crystal oscillator circuit". ? added the description of "sub crystal oscillator". 74 8. block diagram corrected the figure. ? tioa: input input/output ? tiob: output input 75 10.memory map 10.1 memory map (1) corrected the value of address of "sram0". 75 10.2 memory map (2) added the footnote. 78, 79 11. pin status in each cpu state 11.1 list of pin status ? corrected the return from deep standby mode state of "pin status type h". ? corrected the functon group of "pin status type i" . 77, 78 13. electrical characteristics 13.3. dc characteristics 13.3.1 current rating ? revised the value of "tbd". ? revised the typical value of "power supply voltage (i cch , i cct , i ccr )". ? added the "flash memory write/erase current (i ccflash )". ? added the footnote. 94, 95, 13.4. ac characteristics 13.4.2 sub clock input characteristics ? added the description of note of "input frequency (f cl )". ? added the footnote. 13.4.3 built - in cr oscillation characteristics 13.4.3.1 built - in high - speed cr ? reviced the condition. ? corrected the value. ? added the item of "frequency stabilization time". ? added the footnote. 99 13.4.7. external bus timing 13.4.7.1. separate bus access asynchronous sram mode ? corrected the value. ? deleted the "mwex data output time". ? added the "mcsx data output time". ? corrected the figure. 101 13.4.7.2 separate bus access synchronous sram mode ? corrected the "mclk data output time". ? added the "mclk data hold time". ? corrected the figure. 110, 112, 114, 116 13.4.9. csio timming corrected the description of section title. uart timming csio timming corrected the description of "note". uart is connected multi - function serial is connected 122 13.4.12 i 2 c timing added the footnote. 125 13.5. 12 - bit a/d converter ? revised the parameter. ? revised the symbol. ? corrected the value. document number: 002 - 05646 rev.*c page 144 of 147 mb9a150rb series page section change results 127 13.5.2 definition of 12 - bit a/d converter terms ? revised the parameter. ? revised the symbol. 128, 129 13.6. low - voltage detection characteristics 13.6.1 low - voltage detection reset ? corrected "conditions" and "value" in the table. ? added the item. ? added the footnote . 130 13.6.2 interrupt of low - voltage detection added the item. revision 1.1 - - company name and layout design change revision 2.0 - - corrected the series name. mb9a150r series mb9a150ra series - - corrected the product name as follows. mb9af156ma, mb9af155ma, mb9af154ma mb9af156na, mb9af155na, mb9af154na mb9af156ra, mb9af155ra, mb9af154ra 1 features external bus interface added the item. ? maximum area size : up to 256 mbytes 1 multi - function serial interface corrected the description of "i 2 c" 2 multi - function timer corrected the channel count of "a/d activation compare" 7 1.product lineup 1.2 function added the footnote 9 2. packages delete the following packages. ? fpt - 100p - m36 ? fpt - 80p - m40 11 3. pin assignment 3.2 fpt - 100p - m36 delete the item 12 3.3 fpt - 80p - m37 corrected the description of section title. fpt - 80p - m37/m40 fpt - 80p - m37 15 C 36 4. list of pin function 4.1 list of numbers delete column of terminal number "qfp - 100" 37 - 60 4.2 list of pin functions delete column of terminal number "qfp - 100" 75 10.memory map 10.1 memory map (1) corrected the address "external device area" 88 13.electrical characteristics 13.2.recommended operatin g conditions add the footnote 89 13.3.dc characteristics 13.3.1 current rating ? corrected the condition ? delete the minmun value ? corrected the remarks ? add the footnote 116 13.9. csio timing 13.9.4 synchronous serial (spi=1, scinv=1) corrected the figure of "ms bit=1" 117 13.9 csio timing 13.4.9.5. external clock(ext=1):asyntironous only corrected the figure document number: 002 - 05646 rev.*c page 145 of 147 mb9a150rb series page section change results 118 13.4.10. external input timing add the terminal as follows ? frckx ? icxx ? dttixx 122 13.4.12. i 2 c timing corrected the description as follows. ? typical mode standard - mode ? high - speed mode fast - mode 125 13.5.12 - bit a/d converter 13.5.1 electrical characteristics for the a/d converter ? corrected the terminal name an00 to an23 anxx ? corrected the minmum value of "sampling time" ? corrected the max and min value of "state transition time to oprerationpermission" ? corrected the footnote 137 14. ordering informaton corrected the "part number" revision 3.0 - - corrected the series name. mb9a150ra series mb9a150rb series - - corrected the product name as follows. mb9af156mb, mb9af155mb, mb9af154mb mb9af156nb, mb9af155nb, mb9af154nb mb9af156rb, mb9af155rb, mb9af154rb 76 10.memory map 10.2. memory map(2) added the summary of flash memory sector 89 13. electrical characteristics 13.3. dc characteristics 13.3.1 current rating ? changed the table format ? added main timer mode current ? moved a/d converter current 96 13. electrical characteristics 13.4. ac characteristics 13.4.1 operating conditions of main pll 13.4.2 operating conditions of main pll ? added the figure of main pll connection 97 13. electrical characteristics 13. 4. ac characteristics 13.4.6. power - on reset timing ? added time until releasing power - on reset ? changed the figure of timing 110 - 117 13.electrical characteristics 13.4. ac characteristics 13.4.9 csio/uart timing ? modified from uart timing to csio/uart timing ? changed from internal shift clock operation to master mode ? changed from external shift clock operation to slave mode 125 13. elect rical characteristics 13.5. 12bit a/d converter ? added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage ? added the value of conversion time at av cc < 2.7 v 132 - 134 13. electrical characteristics 13.8. return time from low - power consumption mode added return time from low - power consumption mode 137 14. ordering information changed notation of part number 137 - 141 15. package dimensions deleted fpt - 100p - m36 and fpt - 80p - m40 note: please see document history about later revised information. document number: 002 - 05646 rev.*c page 146 of 147 mb9a150rb series document history document title: mb9a150rb series 32 - bit arm? cortex? - m3 fm3 microcontroller document number: 002 - 05646 revision ecn orig. of change submission date description of change ** ? akih 04/28/2015 migrated to cypress and assigned document number 002 - 05646. no change to document contents or format. *a 5226742 akih 04/27/2016 updated to cypress template *b 5 535819 yska 02 / 09 /201 7 updated 12.4. 6 power - on reset timing. changed parameter from power supply rise time(tr)[ms] to power ramp rate(dv/dt)[mv/us] and added some comments ( page 96 ) modified rtc description in features, real - time clock(rtc) as below changed starting count value from 01 to 00. deleted second , or day of the week in the interrupt function ( page 3 ) added notes for jtag ( page 59 ), changed j - tag to jtag in 4.2 list of pin functio ns ( page 4 0 ) updated package code and dimensions as follows ( page 8 - 1 3 , 135 - 140 ) fpt - 80p - m37 - > lqh080, bga - 96p - m07 - > fdg096, fpt - 100p - m23 - > lqi100, bga - 112p - m04 - > lbc112, fpt - 120p - m37 - > lqm120 added 15.errta ( page 141 ) deleted the note below from the footer of the first page. "confidential - released only under nondisclosure agreement (nda)" ( page 1 ) added the baud rate spec in 12.4.9 csio/uart timing( page 109 , 111 , 113 , 115 ) *c 5774754 ysat 06/19/2017 adapted new cypress log o document number: 002 - 05646 rev.*c june 19, 2017 page 147 of 147 mb9a150rb series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, v isit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semiconductor corporation, 2012 - 2017. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress). this document, including any software or firmware included or referenced in this document (software), is owned by cypress under the intell ectual property laws and treat ies of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this para graph, grant any license under its patents, copyrights, trademarks, or other intellect ual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agree ment with cypress governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable lice nse (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organiz ation , and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product unit s, and (2) under those claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress h ardware products. any other use, reproduction, modification, translation, or compilation of the software is prohi bited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this doc ument or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design information or pr ogramming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. cypres s products are not designed, intended, or authorized for use as critical components in systems designed or intended for the ope rat ion of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution con trol or hazardous substances management, or other uses where t he failure of the device or system could cause personal injury, death, or property damage (unintended uses). a critical compo nent is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the devi ce or system, or to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cyp ress.com. other names and brands may be claimed as property of their respective owners. |
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